📄 masks860.h
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/* CP Interrupt In-Service Register (CISR) */
#define CISR_PC15 0x80000000
#define CISR_SCC1 0x40000000
#define CISR_SCC2 0x20000000
#define CISR_SCC3 0x10000000
#define CISR_SCC4 0x08000000
#define CISR_PC14 0x04000000
#define CISR_TIMER1 0x02000000
#define CISR_PC13 0x01000000
#define CISR_PC12 0x00800000
#define CISR_SDMA 0x00400000
#define CISR_IDMA1 0x00200000
#define CISR_IDMA2 0x00100000
#define RESERVED104 0x00080000
#define CISR_TIMER2 0x00040000
#define CISR_R_TT 0x00020000
#define CISR_I2C 0x00010000
#define CISR_PC11 0x00008000
#define CISR_PC10 0x00004000
#define RESERVED105 0x00002000
#define CISR_TIMER3 0x00001000
#define CISR_PC9 0x00000800
#define CISR_PC8 0x00000400
#define CISR_PC7 0x00000200
#define RESERVED106 0x00000100
#define CISR_TIMER4 0x00000080
#define CISR_PC6 0x00000040
#define CISR_SPI 0x00000020
#define CISR_SMC1 0x00000010
#define CISR_SMC2_PIP 0x00000008
#define CISR_PC5 0x00000004
#define CISR_PC4 0x00000002
#define RESERVED107 0x00000001
/* COMMUNICATION PROCESSOR */
/* CPM Command Register (CPCR) */
#define CPCR_RST 0x8000 /* Software Reset Command */
#define RESERVED121 0x7000
#define CPCR_INIT_TX_RX_PARAMS 0x0000 /* Opcode 0 */
#define CPCR_INIT_RX_PARAMS 0x0100 /* Opcode 1 */
#define CPCR_INIT_TX_PARAMS 0x0200 /* Opcode 2 */
#define CPCR_ENTER_HUNT_MODE 0x0300 /* Opcode 3 */
#define CPCR_STOP_TX 0x0400 /* Opcode 4 */
#define CPCR_GRACEFUL_STOP_TX 0x0500 /* Opcode 5 */
#define CPCR_RESTART_TX 0x0600 /* Opcode 6 */
#define CPCR_CLOSE_RX_BD 0x0700 /* Opcode 7 */
#define CPCR_SET_GRP_ADDR 0x0800 /* Opcode 8 */
#define CPCR_RESET_BCS 0x0A00 /* Opcode 10 */
#define CPCR_SCC1_CH 0x0000 /* CPCR ch Num Field: SCC1 */
#define CPCR_I2C_IDMA1_CH 0x0010 /* CPCR ch Num Field: I2C/IDMA1 */
#define CPCR_SCC2_CH 0x0040 /* CPCR Ch Num Field: SCC2 */
#define CPCR_SPI_IDMA2_TIMER_CH 0x0050 /* CPCR Ch Num Field: SPI/IDMA/
RISC Timers */
#define CPCR_SCC3_CH 0x0080 /* CPCR Ch Num Field: SCC3 */
#define CPCR_SMC1_DSP1_CH 0x0090 /* CPCR Ch Num Field: SMC1/DSP1 */
#define CPCR_SCC4_CH 0x00C0 /* CPCR Ch Num Field: SCC4 */
#define CPCR_SMC2_DSP2_CH 0x00D0 /* CPCR Ch Num Field: SMC2/DSP2 */
#define RESERVED122 0x000E
#define CPCR_FLG 0x0001 /* Command Semaphore Flag */
/* RISC Controller Configuration Register (RCCR) */
#define RCCR_TIME 0x8000 /* Timer Enable */
#define RESERVED123 0x4000
#define RCCR_TIMEP 0x3F00 /* Timer Period */
#define RCCR_DR1M 0x0080 /* IDMA Request 1 Mode */
#define RCCR_DR0M 0x0040 /* IDMA Request 0 Mode */
#define RCCR_DRQP 0x0030 /* IDMA Request Priority */
#define RCCR_EIE 0x0008 /* External Interrupt Enable */
#define RCCR_SCD 0x0004 /* Scheduler Configuration */
#define RCCR_ERAM 0x0003 /* Enable RAM Microcode */
/* RISC Timer Event Register (RTER) */
#define RTER_TMR15 0x8000
#define RTER_TMR14 0x4000
#define RTER_TMR13 0x2000
#define RTER_TMR12 0x1000
#define RTER_TMR11 0x0800
#define RTER_TMR10 0x0400
#define RTER_TMR9 0x0200
#define RTER_TMR8 0x0100
#define RTER_TMR7 0x0080
#define RTER_TMR6 0x0040
#define RTER_TMR5 0x0020
#define RTER_TMR4 0x0010
#define RTER_TMR3 0x0008
#define RTER_TMR2 0x0004
#define RTER_TMR1 0x0002
#define RTER_TMR0 0x0001
/* RISC Timer Mask Register (RTMR) */
#define RTMR_TMR15 0x8000
#define RTMR_TMR14 0x4000
#define RTMR_TMR13 0x2000
#define RTMR_TMR12 0x1000
#define RTMR_TMR11 0x0800
#define RTMR_TMR10 0x0400
#define RTMR_TMR9 0x0200
#define RTMR_TMR8 0x0100
#define RTMR_TMR7 0x0080
#define RTMR_TMR6 0x0040
#define RTMR_TMR5 0x0020
#define RTMR_TMR4 0x0010
#define RTMR_TMR3 0x0008
#define RTMR_TMR2 0x0004
#define RTMR_TMR1 0x0002
#define RTMR_TMR0 0x0001
/* SCC1 */
/* SCC1 General Mode Register (GSMR_L1) */
#define GSMR_L1_SIR 0x80000000 /* Serial Infrared Encoding */
#define GSMR_L1_EDGE 0x60000000 /* Clock Edge */
#define GSMR_L1_TCI 0x10000000 /* Transmit Clock Invert */
#define GSMR_L1_TSNC 0x0C000000 /* Transmit Sense */
#define GSMR_L1_RINV 0x02000000 /* DPLL Receive Input Invert Data */
#define GSMR_L1_TINV 0x01000000 /* DPLL Transmit Input Invert Data */
#define GSMR_L1_TPL 0x00E00000 /* Tx Preamble Length */
#define GSMR_L1_TPP 0x00180000 /* Tx Preamble Pattern */
#define GSMR_L1_TEND 0x00040000 /* Transmitter Frame Ending */
#define GSMR_L1_TDCR 0x00030000 /* Transmit Divide Clock Rate */
#define GSMR_L1_RDCR 0x0000C000 /* Receive DPLL Clock Rate */
#define GSMR_L1_RENC 0x00003800 /* Receiver Decoding Method */
#define GSMR_L1_TENC 0x00000700 /* Transmitter Encoding Method */
#define GSMR_L1_DIAG 0x000000C0 /* Diagnostic Mode */
#define GSMR_L1_INT_LB 0x00000040 /* Internal Loopback mask */
#define GSMR_L1_ENR 0x00000020 /* Enable Receive */
#define GSMR_L1_ENT 0x00000010 /* Enable Transmit */
#define GSMR_L1_MODE 0x0000000F /* Channel Protocol Mode */
/* SCC1 General Mode Register (GSMR_H1) */
#define RESERVED128 0xFFF80000
#define GSMR_H1_IRP 0x00040000 /* Infrared Rx Polarity */
#define RESERVED129 0x00020000
#define GSMR_H1_GDE 0x00010000 /* Glitch Detect Enable */
#define GSMR_H1_TCRC 0x0000C000 /* Transparent CRC */
#define GSMR_H1_REVD 0x00002000 /* Reverse Data */
#define GSMR_H1_TRX 0x00001000 /* Transparent Receiver */
#define GSMR_H1_TTX 0x00000800 /* Transparent Transmitter */
#define GSMR_H1_CDP 0x00000400 /* CD Pulse */
#define GSMR_H1_CTSP 0x00000200 /* CTS Pulse */
#define GSMR_H1_CDS 0x00000100 /* CD Sampling */
#define GSMR_H1_CTSS 0x00000080 /* CTS Sampling */
#define GSMR_H1_TFL 0x00000040 /* Transmit FIFO Length */
#define GSMR_H1_RFW 0x00000020 /* Rx FIFO Width */
#define GSMR_H1_TXSY 0x00000010 /* Transmitter Synched to Receiver */
#define GSMR_H1_SYNL 0x0000000C /* Sync Length */
#define GSMR_H1_RTSM 0x00000002 /* RTS mode */
#define GSMR_H1_RSYN 0x00000001 /* Receive Sync Timing */
/* SCC1 Transmit_On-Demand Register (TODR1) */
#define TODR1_TOD 0x8000 /* Transmit on Demand */
#define RESERVED130 0x0FFF
/* SCC1 Data Synchronization Register (DSR1) */
#define DSR1_SYN2 0xFF00
#define DSR1_SYN1 0x00FF
#define DSR_ENET 0xD555
#define DSR_HDLC 0x7E7E /* SCC Data Synch. Reg. */
/* SCC2 */
/* SCC2 General Mode Register (GSMR_L2) */
#define GSMR_L2_SIR 0x80000000 /* Serial Infrared Encoding */
#define GSMR_L2_EDGE 0x60000000 /* Clock Edge */
#define GSMR_L2_TCI 0x10000000 /* Transmit Clock Invert */
#define GSMR_L2_TSNC 0x0C000000 /* Transmit Sense */
#define GSMR_L2_RINV 0x02000000 /* DPLL Receive Input Invert Data */
#define GSMR_L2_TINV 0x01000000 /* DPLL Transmit Input Invert Data */
#define GSMR_L2_TPL 0x00E00000 /* Tx Preamble Length */
#define GSMR_L2_TPP 0x00180000 /* Tx Preamble Pattern */
#define GSMR_L2_TEND 0x00040000 /* Transmitter Frame Ending */
#define GSMR_L2_TDCR 0x00030000 /* Transmit Divide Clock Rate */
#define GSMR_L2_RDCR 0x0000C000 /* Receive DPLL Clock Rate */
#define GSMR_L2_RENC 0x00003800 /* Receiver Decoding Method */
#define GSMR_L2_TENC 0x00000700 /* Transmitter Encoding Method */
#define GSMR_L2_DIAG 0x000000C0 /* Diagnostic Mode */
#define GSMR_L2_ENR 0x00000020 /* Enable Receive */
#define GSMR_L2_ENT 0x00000010 /* Enable Transmit */
#define GSMR_L2_MODE 0x0000000F /* Channel Protocol Mode */
/* SCC2 General Mode Register (GSMR_H2) */
#define RESERVED131 0xFFF80000
#define GSMR_H2_IRP 0x00040000 /* Infrared Rx Polarity */
#define RESERVED132 0x00020000
#define GSMR_H2_GDE 0x00010000 /* Glitch Detect Enable */
#define GSMR_H2_TCRC 0x0000C000 /* Transparent CRC */
#define GSMR_H2_REVD 0x00002000 /* Reverse Data */
#define GSMR_H2_TRX 0x00001000 /* Transparent Receiver */
#define GSMR_H2_TTX 0x00000800 /* Transparent Transmitter */
#define GSMR_H2_CDP 0x00000400 /* CD Pulse */
#define GSMR_H2_CTSP 0x00000200 /* CTS Pulse */
#define GSMR_H2_CDS 0x00000100 /* CD Sampling */
#define GSMR_H2_CTSS 0x00000080 /* CTS Sampling */
#define GSMR_H2_TFL 0x00000040 /* Transmit FIFO Length */
#define GSMR_H2_RFW 0x00000020 /* Rx FIFO Width */
#define GSMR_H2_TXSY 0x00000010 /* Transmitter Synched to Receiver */
#define GSMR_H2_SYNL 0x0000000C /* Sync Length */
#define GSMR_H2_RTSM 0x00000002 /* RTS mode */
#define GSMR_H2_RSYN 0x00000001 /* Receive Sync Timing */
/* SCC2 Transmit_On-Demand Register (TODR2) */
#define TODR2_TOD 0x8000 /* Transmit on Demand */
#define RESERVED133 0x0FFF
/* SCC2 Data Synchronization Register (DSR2) */
#define DSR2_SYN2 0xFF00
#define DSR2_SYN1 0x00FF
/* SCC3 */
/* SCC3 General Mode Register (GSMR_L3) */
#define GSMR_L3_SIR 0x80000000 /* Serial Infrared Encoding */
#define GSMR_L3_EDGE 0x60000000 /* Clock Edge */
#define GSMR_L3_TCI 0x10000000 /* Transmit Clock Invert */
#define GSMR_L3_TSNC 0x0C000000 /* Transmit Sense */
#define GSMR_L3_RINV 0x02000000 /* DPLL Receive Input Invert Data */
#define GSMR_L3_TINV 0x01000000 /* DPLL Transmit Input Invert Data */
#define GSMR_L3_TPL 0x00E00000 /* Tx Preamble Length */
#define GSMR_L3_TPP 0x00180000 /* Tx Preamble Pattern */
#define GSMR_L3_TEND 0x00040000 /* Transmitter Frame Ending */
#define GSMR_L3_TDCR 0x00030000 /* Transmit Divide Clock Rate */
#define GSMR_L3_RDCR 0x0000C000 /* Receive DPLL Clock Rate */
#define GSMR_L3_RENC 0x00003800 /* Receiver Decoding Method */
#define GSMR_L3_TENC 0x00000700 /* Transmitter Encoding Method */
#define GSMR_L3_DIAG 0x000000C0 /* Diagnostic Mode */
#define GSMR_L3_ENR 0x00000020 /* Enable Receive */
#define GSMR_L3_ENT 0x00000010 /* Enable Transmit */
#define GSMR_L3_MODE 0x0000000F /* Channel Protocol Mode */
/* SCC3 General Mode Register (GSMR_H3) */
#define RESERVED134 0xFFF80000
#define GSMR_H3_IRP 0x00040000 /* Infrared Rx Polarity */
#define RESERVED135 0x00020000
#define GSMR_H3_GDE 0x00010000 /* Glitch Detect Enable */
#define GSMR_H3_TCRC 0x0000C000 /* Transparent CRC */
#define GSMR_H3_REVD 0x00002000 /* Reverse Data */
#define GSMR_H3_TRX 0x00001000 /* Transparent Receiver */
#define GSMR_H3_TTX 0x00000800 /* Transparent Transmitter */
#define GSMR_H3_CDP 0x00000400 /* CD Pulse */
#define GSMR_H3_CTSP 0x00000200 /* CTS Pulse */
#define GSMR_H3_CDS 0x00000100 /* CD Sampling */
#define GSMR_H3_CTSS 0x00000080 /* CTS Sampling */
#define GSMR_H3_TFL 0x00000040 /* Transmit FIFO Length */
#define GSMR_H3_RFW 0x00000020 /* Rx FIFO Width */
#define GSMR_H3_TXSY 0x00000010 /* Transmitter Synched to Receiver */
#define GSMR_H3_SYNL 0x0000000C /* Sync Length */
#define GSMR_H3_RTSM 0x00000002 /* RTS mode */
#define GSMR_H3_RSYN 0x00000001 /* Receive Sync Timing */
/* SCC3 Transmit_On-Demand Register (TODR3) */
#define TODR3_TOD 0x8000 /* Transmit on Demand */
#define RESERVED136 0x0FFF
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