masks860.h

基于vxworks操作系统的电话语音平台系统

#define MAMR_DSA         0x00060000   /* Disable Timer Period */
#define RESERVED64       0x00010000   
#define MAMR_G0CLA       0x0000E000   /* General Line 0 Control A */
#define MAMR_GPLA_A4DIS	 0x00001000   /* GPL_A4 Output Disable Line */
#define MAMR_RLFA        0x00000F00   /* Read Loop Field A */
#define MAMR_WLFA        0x000000F0   /* Write Loop Field A */
#define MAMR_TLFA        0x0000000F   /* Timer Loop Field A */ 



/*  Machine B Mode Register (MBMR) */
#define MBMR_PTB        0xFF000000   /* Periodic Timer B Period */
#define MBMR_PTBE       0x00800000   /* Periodic Timer B Enable */
#define MBMR_AMB        0x00700000   /* Address Multiplex Size B */
#define RESERVED65      0x00080000
#define MBMR_DSB        0x00060000   /* Disable Timer Period */
#define RESERVED66      0x00010000  
#define MBMR_G0CLB      0x0000E000   /* General Line 0 Control B */
#define MBMR_GPL_B4DIS	0x00001000   /* GPL_B4 Output Line Disable */
#define MBMR_RLFB       0x00000F00   /* Read Loop Field B */
#define MBMR_WLFB       0x000000F0   /* Write Loop Field B */
#define MBMR_TLFB       0x0000000F   /* Timer Loop Field B */



/* Memory Status Register (MSTAT) */
#define MSTAT_PER0   0x8000   /* Parity Error Bank 0 */
#define MSTAT_PER1   0x4000   /* Parity Error Bank 1 */
#define MSTAT_PER2   0x2000   /* Parity Error Bank 2 */
#define MSTAT_PER3   0x1000   /* Parity Error Bank 3 */
#define MSTAT_PER4   0x0800   /* Parity Error Bank 4 */
#define MSTAT_PER5   0x0400   /* Parity Error Bank 5 */
#define MSTAT_PER6   0x0200   /* Parity Error Bank 6 */
#define MSTAT_PER7   0x0100   /* Parity Error Bank 7 */
#define MSTAT_WPER   0x0080   /* Write Protection Error */
#define RESERVED67   0x007F   


/* Memory Periodic Timer Prescaler Register (MPTPR) */
#define MPTPR_PTP    0xFF00   /* Periodic Timers Prescaler */
#define RESERVED68   0x00FF	  



/*                        SYSTEM INTEGRATION TIMERS                                        */
/* Timers Timebase Status and Control Register (TBSCR) */
#define TBSCR_TBIRQ   0xFF00   /* Timebase Interrupt Request */
#define TBSCR_REFA    0x0080   /* Reference Interrupt Status */
#define TBSCR_REFB    0x0040   /* Reference Interrupt Status */
#define RESERVED69    0x0030  
#define TBSCR_REFAE   0x0008   /* Refernce Interrupt Enable */
#define TBSCR_REFBE   0x0004   /* Refernce Interrupt Enable */
#define TBSCR_TBF     0x0002   /* Timebase Freeze */
#define TBSCR_TBE     0x0001   /* Timebase Enable */

/* Timebase Reference Register 0 (TBREFF0)                            */
#define TBREFF0_TBREF   0xFFFFFFFF
#define TBREFF1_TBREF   0xFFFFFFFF



/* Real-Time Clock Status and Control Register (RTCSC) */
#define RTCSC_RTCIRQ    0xFF00   /* RTC Interrupt Request */
#define RTCSC_SEC       0x0080   /* Once Per Second Interrupt */
#define RTCSC_ALR       0x0040   /* Alarm Interrupt */
#define RESERVED70      0x0020  
#define RTCSC_38K       0x0010   /* Real_time Clock Source Select */
#define RTCSC_SIE       0x0008   /* Second interrupt Enable */
#define RTCSC_ALE       0x0004   /* Alarm Interrupt Enable */
#define RTCSC_RTF       0x0002   /* Real-Time Clock Freeze */
#define RTCSC_RTE       0x0001   /* Real-Time Clock Enable */

/*  Real-Time Clock Register (RTC)                           */
#define RTC_RTC   0xFFFFFFFF   



/* Real-Time Clock Alarm Register (RTCAL)                    */
#define RTCAL_ALARM  0xFFFFFFFF   


/*  Periodic Interrupt Status and Control Register (PISCR) */
#define PISCR_PIRQ   0xFF00   /* Periodic Interrupt Request Level */
#define PISCR_PS     0xFF80   /* Periodic Interrupt Status */
#define RESERVED71   0x0078  
#define PISCR_PIE    0x0004   /* Periodic Interrupt Enable */
#define PISCR_PITF   0x0002   /* Periodic Interrupt Timer Freeze */
#define PISCR_PTE    0x0001   /* Periodic Timer Enable */



/*  Periodic Interrupt Timer Count (PITC)                         */
#define PITC_PITC   0xFFFF0000
#define RESERVED72  0x0000FFFF

/*  Periodic Interrupt Timer Register (PITR)                       */
#define PITR_PIT    0xFFFF0000
#define RESERVED73  0x0000FFFF




/* System Clock Control register (SCCR) */
#define RESERVED74   0x80000000
#define SCCR_COM     0x60000000	/* Clock Output Mode */
#define RESERVED75   0x1C000000
#define SCCR_TBS     0x02000000    /* Timebase Source */
#define SCCR_RTDIV   0x01000000    /* RTC Clock Divide */
#define SCCR_RTSEL   0x00800000    /* RTC circuit input source select */
#define SCCR_CRQEN   0x00400000    /* CPM requect enable */
#define SCCR_PRQEN   0x00200000    /* Power management request enable */
#define RESERVED76   0x00180000  
#define SCCR_EBDF    0x00060000    /* CLKOUT frequency */
#define RESERVED77   0x00018000    
#define SCCR_DFSYNC  0x00006000    /* Division factor of SyncCLK */
#define SCCR_DFBRG   0x00001800    /* Division factor of BRGCLK */
#define SCCR_DFNL    0x00000700    /* Division factor low frequency */
#define SCCR_DFNH    0x000000D0    /* Division factor high frequency */
#define RESERVED78   0x0000001F 



/* PLL, Low Power, and Reset Control Register (PLPRCR) */
#define PLPRCR_MF      0xFFF00000   /* Multiplication factor bits */
#define RESERVED79     0x000F0000
#define PLPRCR_SPLSS   0x00008000   /* SPLL lock status sticky bits */
#define PLPRCR_TEXPS   0x00004000   /* TEXP status bit */
#define RESERVED80     0x00002000   
#define PLPRCR_TMIST   0x00001000   /* Timers interrupt status */
#define RESERVED81     0x00000800   
#define PLPRCR_CSRC    0x00000400   /* Clock source bit */
#define PLPRCR_LPM     0x00000300   /* Low power mode select bits */
#define PLPRCR_CSR     0x00000080   /* Checkstop reset enable */
#define PLPRCR_LOLRE   0x00000040   /* Loss of lock reset enable */
#define PLPRCR_FIOPD   0x00000020   /* Force I/O pull-down */
#define RESERVED82     0x0000001F

/* Reset status register (RSR) */
#define RSR_EHRS    0x80	  /* External hard reset status */
#define RSR_ESRS    0x40	  /* External soft reset status */
#define RSR_LLRS    0x20     /* Loss of lock status */
#define RSR_SWRS    0x10     /* Software watchdog reset status */
#define RSR_CSRS    0x08     /* Check stop reset status */
#define RSR_DBHRS   0x04     /* Debug port hard reset status */
#define RSR_DBSRS   0x02     /* Debug port soft reset status */
#define RSR_JTRS    0x01     /* JTAG reset status */


/*-------------------------------------------------------------------------*
 *                                    DMA 								   *
 *-------------------------------------------------------------------------*/
/*   SDMA Status Register (SDSR)     */
#define SDSR_SBER    0x80   /* SDMA Channel Bus Error */
#define SDSR_RINT    0x40   /* Reserved Interrupt */
#define RESERVED90   0x3C   
#define SDSR_DSP2    0x02   /* DSP Chain 2 Interrupt */
#define SDSR_DSP1    0x01   /* DSP Chain 1 Interrupt */
       


/*  IDMA1 Status Register (IDSR1)     */
#define RESERVED91   0xF8
#define IDSR1_OB     0x04   /* Out of buffers */
#define IDSR1_DONE   0x02   /* IDMA transfer done */		
#define IDSR1_AD     0x01   /* Auxiliary done */

/*  IDMA1 Mask Register (IDMR1)                                                                         */


/*  IDMA2 Status Register (IDSR2)     */
#define RESERVED92   0xF8
#define IDSR2_OB     0x04   /* Out of buffers */
#define IDSR2_DONE   0x02   /* IDMA transfer done */		
#define IDSR3_AD     0x01   /* Auxiliary done */

/*-------------------------------------------------------------------------*
 *                          CPM INTERRUPT CONTROL						   *
 *-------------------------------------------------------------------------*/
/* CP Interrupt Vector Register (CIVR)     */
#define CIVR_VN      0xF800   /* Vector number */
#define RESERVED93	0x07FE
#define CIVR_IACK    0x0001   /* Interrupt acknowledge */

/*  CP Interrupt Configuration Register (CICR)                       */
#define RESERVED94   0xFF000000
#define CICR_SDdP    0x00C00000   /* SCCd priority order */
#define CICR_SCcP    0x00300000   /* SCCc priority order */
#define CICR_SCbP    0x000C0000   /* SCCb priority order */
#define CICR_SCaP    0x00030000   /* SCCa priority order */
#define CICR_IRL0    0x00008000   /* Interrupt request level */
#define CICR_IRL1    0x00004000   /* Interrupt request level */
#define CICR_IRL2    0x00002000   /* Interrupt request level */
#define CICR_HP0     0x00001000   /* Highest priority */
#define CICR_HP1     0x00000800   /* Highest priority */
#define CICR_HP2     0x00000400   /* Highest priority */
#define CICR_HP3     0x00000200   /* Highest priority */
#define CICR_HP4     0x00000100   /* Highest priority */
#define RESERVED95   0x0000007E 
#define CICR_SPS     0x00000001   /* Spread priority scheme */


/* CP Interrupt Pending Register (CIPR)                               */
#define CIPR_PC15      0x80000000   
#define CIPR_SCC1      0x40000000
#define CIPR_SCC2      0x20000000
#define CIPR_SCC3      0x10000000
#define CIPR_SCC4      0x08000000
#define CIPR_PC14      0x04000000
#define CIPR_TIMER1    0x02000000
#define CIPR_PC13      0x01000000
#define CIPR_PC12      0x00800000
#define CIPR_SDMA      0x00400000
#define CIPR_IDMA1     0x00200000
#define CIPR_IDMA2     0x00100000
#define RESERVED96     0x00080000
#define CIPR_TIMER2    0x00040000
#define CIPR_R_TT      0x00020000
#define CIPR_I2C       0x00010000
#define CIPR_PC11      0x00008000
#define CIPR_PC10      0x00004000
#define RESERVED97     0x00002000
#define CIPR_TIMER3    0x00001000
#define CIPR_PC9       0x00000800
#define CIPR_PC8       0x00000400
#define CIPR_PC7       0x00000200
#define RESERVED98     0x00000100
#define CIPR_TIMER4    0x00000080
#define CIPR_PC6       0x00000040
#define CIPR_SPI       0x00000020
#define CIPR_SMC1      0x00000010
#define CIPR_SMC2_PIP  0x00000008
#define CIPR_PC5       0x00000004
#define CIPR_PC4       0x00000002
#define RESERVED99     0x00000001



/*  CP Interrupt Mask Register (CIMR)                                    */
#define CIMR_PC15      0x80000000   
#define CIMR_SCC1      0x40000000
#define CIMR_SCC2      0x20000000
#define CIMR_SCC3      0x10000000
#define CIMR_SCC4      0x08000000
#define CIMR_PC14      0x04000000
#define CIMR_TIMER1    0x02000000
#define CIMR_PC13      0x01000000
#define CIMR_PC12      0x00800000
#define CIMR_SDMA      0x00400000
#define CIMR_IDMA1     0x00200000
#define CIMR_IDMA2     0x00100000
#define RESERVED100    0x00080000
#define CIMR_TIMER2    0x00040000
#define CIMR_R_TT      0x00020000
#define CIMR_I2C       0x00010000
#define CIMR_PC11      0x00008000
#define CIMR_PC10      0x00004000
#define RESERVED101    0x00002000
#define CIMR_TIMER3    0x00001000
#define CIMR_PC9       0x00000800
#define CIMR_PC8       0x00000400
#define CIMR_PC7       0x00000200
#define RESERVED102    0x00000100
#define CIMR_TIMER4    0x00000080
#define CIMR_PC6       0x00000040
#define CIMR_SPI       0x00000020
#define CIMR_SMC1      0x00000010
#define CIMR_SMC2_PIP  0x00000008
#define CIMR_PC5       0x00000004
#define CIMR_PC4       0x00000002
#define RESERVED103    0x00000001