masks860.h

基于vxworks操作系统的电话语音平台系统

/*------------------------------------------------------------------------*
 *  FILE:  MASKS860.H                                                     *
 *          														      *
 *  DESCRIPTION:  Bit masks for MPC860 registers. Sequence of registers   *
 *                follows device memory map exactly. 				      *
 *																		  * 
 *  REGISTERS NOT														  *
 *  INCLUDED:  SWSR, SCCRK, PLPRCRK, RSRK, SDAR, SDMR, IDMR1, IDMR2,      *
 *				   TRR1-4, TCR1-4, TCN1-4, PSMR1, SCCE1, SCCM1, SCCS1,    *
 *             PSMR2, PSMR3, SCCE3, SCCM3, SCCS3, PSMR4, SCCE4,	          *
 *             SCCM4, SCCS4, SIRP				         			      *
 *																		  *
 *  Note: Look in the Protocol Specific section below first before        *
 *        determining that the above registers are not covered.           *
 *										    							  * 
 *																		  *
                            GENERAL PURPOSE MASKS                        */               
#define  ALL_ONES    0xFFFFFFFF
#define  ALL_ZEROS   0x00000000


/*  GENERAL SIU      */                                                                                                                        
/*  Module Configuration Register (SIUMCR) */
#define SIUMCR_EARB  0x80000000   /* External Arbitration */
#define SIUMCR_EARP  0x70000000   /* External Arbitration Req. Priority */
#define RESERVED1    0x0F000000   
#define SIUMCR_DSHW  0x00800000   /* Data Show Cycles */
#define SIUMCR_DBGC  0x00600000   /* Debug Pins Configuration */
#define SIUMCR_DBPC  0x00180000   /* Debug Port Pins Configuration */
#define RESERVED2    0x00040000       
#define SIUMCR_FRC   0x00020000   /* FRZ Pin configuration */
#define SIUMCR_DLK   0x00010000   /* Debug Register Lock */
#define SIUMCR_PNCS  0x00008000   /* Parity Enable Nonmemory Controller
                                      Regions */  
#define SIUMCR_OPAR  0x00004000   /* Odd Parity */
#define SIUMCR_DPC   0x00002000   /* Data Parity Pins Configuration */
#define SIUMCR_MPRE  0x00001000   /* Multiprocessors Reservation Enable */
#define SIUMCR_MLRC  0x00000C00   /* Multi-Level Reservation Control */
#define SIUMCR_AEME  0x00000200   /* Asynchronous External Master Enable */
#define SIUMCR_SEME  0x00000100   /* Synchronous External Master Enable */
#define SIUMCR_BSC   0x00000080   /* Byte Select Configuration */
#define SIUMCR_GB5E  0x00000040   /* GPL_B(5) Enable */
#define SIUMCR_B2DD  0x00000020   /* Bank 2 Double Drive */
#define SIUMCR_B3DD  0x00000010   /* Bank 3 Double Drive */
#define RESERVED3    0x0000000F        

/* System Protection Control Register (SYPCR)           */
#define SYPCR_SWTC  0xFFFF0000     /* SoftWare Watchdog Timer Count */
#define SYPCR_BMT   0x0000FF00     /* Bus Monitor Timing */
#define SYPCR_BME   0x00000080     /* Bus Monitor Enable */
#define RESERVED4   0x00000070
#define SYPCR_SWF   0x00000008     /* Software Watchdog Freeze */
#define SYPCR_SWE   0x00000004     /* Software Watchdog Enable */
#define SYPCR_SWRI  0x00000002     /* Software Watchdog Reset/Interrupt 
                                       Select */
#define SYPCR_SWP   0x00000001     /* Software Watchdog Prescale */


/* Interrupt Pending Register (SIPEND) */
#define SIPEND_IRQ0  0x80000000
#define SIPEND_LVL0  0x40000000
#define SIPEND_IRQ1  0x20000000
#define SIPEND_LVL1  0x10000000
#define SIPEND_IRQ2  0x08000000
#define SIPEND_LVL2  0x04000000
#define SIPEND_IRQ3  0x02000000
#define SIPEND_LVL3  0x01000000
#define SIPEND_IRQ4  0x00800000
#define SIPEND_LVL4  0x00400000
#define SIPEND_IRQ5  0x00200000
#define SIPEND_LVL5  0x00100000
#define SIPEND_IRQ6  0x00080000
#define SIPEND_LVL6  0x00040000
#define SIPEND_IRQ7  0x00020000
#define SIPEND_LV7   0x00010000
#define RESERVED5    0x0000FFFF


/*   SIU Interrupt Mask Register (SIMASK)  */
#define SIMASK_IRM0  0x80000000
#define SIMASK_LVM0  0x40000000
#define SIMASK_IRM1  0x20000000
#define SIMASK_LVM1  0x10000000
#define SIMASK_IRM2  0x08000000
#define SIMASK_LVM2  0x04000000
#define SIMASK_IRM3  0x02000000
#define SIMASK_LVM3  0x01000000
#define SIMASK_IRM4  0x00800000
#define SIMASK_LVM4  0x00400000
#define SIMASK_IRM5  0x00200000
#define SIMASK_LVM5  0x00100000
#define SIMASK_IRM6  0x00080000
#define SIMASK_LVM6  0x00040000
#define SIMASK_IRM7  0x00020000
#define SIMASK_LVM7  0x00010000
#define RESERVED6    0x0000FFFF

/* SIEL Register */
#define SIEL_ED0   0x80000000      
#define SIEL_WM0   0x40000000
#define SIEL_ED1   0x20000000
#define SIEL_WM1   0x10000000
#define SIEL_ED2   0x08000000
#define SIEL_WM2   0x04000000
#define SIEL_ED3   0x02000000
#define SIEL_WM3   0x01000000
#define SIEL_ED4   0x00800000
#define SIEL_WM4   0x00400000
#define SIEL_ED5   0x00200000
#define SIEL_WM5   0x00100000
#define SIEL_ED6   0x00080000
#define SIEL_WM6   0x00040000
#define SIEL_ED7   0x00020000
#define SIEL_WM7   0x00010000
#define RESERVED7  0x0000FFFF

/* SIU Interrupt Vector Register (SIVEC) */
#define SIVEC_INTCODE   0xFF000000  /* Interrupt Code */

/* Transfer Error Status Register (TESR) */
#define RESERVED8  0xC000
#define TESR_IEXT  0x2000    /* Instruction External Transfer Error Acknowledge */
#define TESR_IBM   0x1000    /* Instruction transfer Monitor Timeout */ 
#define TESR_IPB0  0x0800    /* Instruction Parity Error on Byte */
#define TESR_IPB1  0x0400    /* Instruction Parity Error on Byte */
#define TESR_IPB2  0x0200    /* Instruction Parity Error on Byte */
#define TESR_IPB3  0x0100    /* Instruction Parity Error on Byte */
#define RESERVED9  0x00C0   
#define TESR_DEXT  0x0020    /* Data External Transfer Error Acknowledge */
#define TESR_DBM   0x0010    /* Data Transfer Monitor Timeout */
#define TESR_DPB0  0x0008    /* Data Parity Error on Byte */
#define TESR_DPB1  0x0004    /* Data Parity Error on Byte */
#define TESR_DPB2  0x0002    /* Data Parity Error on Byte */
#define TESR_DPB3  0x0001    /* Data Parity Error on Byte */ 

/*  SDMA Configuration Register (SDCR) */
#define RESERVED10   0xFFFF8000    
#define SDCR_FRZ     0x00006000   /* Freeze */
#define RESERVED11   0x00001FF0
#define RESERVED12   0x000000C0
#define SDCR_RAID    0x00000003   /* RISC Controller Arbitration ID */

/* Interface General Control Register A (PGCRA) */
#define PGCRA_CAIREQLVL  0xFF000000   /* Define Interrupt Level for IREQ for Card A */
#define PGCRA_CASCHLVL   0x00FF0000   /* Define Interupt Level for STSCHG for Card A */
#define PGCRA_CADREQ     0x0000C000   /* Define pin to be used as internal DMA request */
#define RESERVED29       0x00003F00   
#define PGCRA_CAOE       0x00000080   /* Card A Output Enable */
#define PGCRA_CARESET    0x00000040   /* Card A Reset */

#define RESERVED30       0x0000003F  

/* Interface General Control Register B (PGCRB) */
#define PGCRB_CBIRQLVL   0xFF000000   /* Define Interrupt Level for IREQ for Card B */
#define PGCRB_CBSCHLVL   0x00FF0000   /* Define Interupt Level for STSCHG for Card B */
#define PGCRB_CBDREQ     0x0000C000   /* Define pin to be used as internal DMA request */
#define RESERVED31       0x00003F00   
#define PGCRB_CBOE       0x00000080   /* Card B Output Enable */
#define PGCRB_CBRESET    0x00000040   /* Card B Reset */

#define RESERVED32       0x0000003F  

/* Interface Status Changed Register (PSCR) */
#define PSCR_CAVS1_C     0x80000000   /* Volt. Sense 1 for Card A changed */
#define PSCR_CAVS2_C     0x40000000   /* Volt. Sense 2 for Card A changed */
#define PSCR_CAWP_C      0x20000000   /* Write Protect for Card A changed */
#define PSCR_CACD2_C     0x10000000   /* Card Detect 2 for Card A changed */
#define PSCR_CACD1_C     0x08000000   /* Card Detect 1 for Card A changed */
#define PSCR_CABVD2_C    0x04000000   /* Batt Volt/SPKR in Card A changed */
#define PSCR_CABVD1_C    0x02000000   /* Batt Volt/STSCHG Card A changed */
#define RESERVED33       0x01000000
#define PSCR_CARDY_L     0x00800000   /* RDY/IRQ of Card A Pin is Low */
#define PSCR_CARDY_H     0x00400000   /* RDY/IRQ of CARD A Pin is High */
#define PSCR_CARDY_R     0x00200000   /* RDY/IRQ of Card A Pin Rising Edge 
                                          detected */
#define PSCR_CARDY_F     0x00100000   /* RDY/IRQ of Card A Pin Falling Edge 
                                          detected */
#define RESERVED34       0x000F0000
#define PSCR_CBVS1_C     0x00008000   /* Volt Sense 1 for Card B changed */
#define PSCR_CBVS2_C     0x00004000   /* Volt Sense 2 for Card B changed */
#define PSCR_CBWP_C      0x00002000   /* Write Protect for Card B changed */
#define PSCR_CBCD2_C     0x00001000   /* Card detect 2 for Card B changed */
#define PSCR_CBCD1_C     0x00000800   /* Card detect 1 for Card B changed */
#define PSCR_CBBVD2_C    0x00000400   /* Batt Volt/SPKR in for Card B 
                                          change */
#define PSCR_CBBVD1_C    0x00000200   /* Batt Volt/STSCHG in for Card B 
                                          change */
#define RESERVED35       0x00000100   
#define PSCR_CBRDY_L     0x00000080   /* RDY/IRQ of Card B Pin is Low */
#define PSCR_CBRDY_H     0x00000040   /* RDY/IRQ of Card B Pin is High */
#define PSCR_CBRDY_R     0x00000020   /* RDY/IRQ of Card B Pin Rising 
                                          Edge detect */
#define PSCR_CBRDY_F     0x00000010   /* RDY/IRQ of Card B Pin Falling
                                          Edge detect */
#define RESERVED36       0x0000000F  



/*  Interface Input Pins Register (PIPR) */
#define PIPR_CAVS1   0x80000000   /* Volt Sense 1 for Card A */
#define PIPR_CAVS2   0x40000000   /* Volt Sense 2 for Card A */
#define PIPR_CAWP    0x20000000   /* Write Protect for Card A */
#define PIPR_CACD2   0x10000000   /* Card Detect 2 for Card A */
#define PIPR_CACD1   0x08000000   /* Card Detect 1 for Card A */
#define PIPR_CABVD2  0x04000000   /* Batt Volt/SPKR in for Card A */
#define PIPR_CABVD1  0x02000000   /* Batt Volt/STSCHG in for Card A */
#define PIPR_CARDY   0x01000000   /* RDY/IRQ of Card A Pin */
#define RESERVED37   0x00FF0000
#define PIPR_CBVS1   0x00008000   /* Voltage Sense 1 for Card B */
#define PIPR_CBVS2   0x00004000   /* Voltage Sense 2 for Card B */
#define PIPR_CBWP    0x00002000   /* Write Protect for Card B */
#define PIPR_CBCD2   0x00001000   /* Card Detect 2 for Card B */
#define PIPR_CBCD1   0x00000800   /* Card Detect 1 for Card B */
#define PIPR_CBBVD2  0x00000400   /* Batt Volt/SPKR in for Card B */
#define PIPR_CBBVD1  0x00000200   /* Batt Volt/STSCHG in for Card B */
#define PIPR_CBRDY   0x00000100   /* RDY/IRQ of Card B Pin */
#define RESERVED38   0x000000FF   
                              


/* Interface Enable Register (PER) */
#define PER_CA_EVS1   0x80000000   /* Enable Volt Sense 1 Card A changed */
#define PER_CA_EVS2   0x40000000   /* Enable Volt Sense 2 Card A changed */
#define PER_CA_EWP    0x20000000   /* Enable Write Prot. Card A Changed */
#define PER_CA_ECD2   0x10000000	/* Enable Card Detect 2 Card A Changed */
#define PER_CA_ECD1   0x08000000   /* Enable Card Detect 2 Card A Changed */
#define PER_CA_EBVD2  0x04000000   /* Enable Batt Volt/SPKR in for Card A changed */
#define PER_CA_EBVD1  0x02000000   /* Enable for Batt Volt/STSCHG in for Card A changed */
#define RESERVED39    0x01000000
#define PER_CA_ERDY_L 0x00800000   /* Enable for RDY/IRQ Card A Pin Low */
#define PER_CA_ERDY_H 0x00400000   /* Enable for RDY/IRQ Card A Pin High */
#define PER_CA_ERDY_R 0x00200000   /* Enable for RDY/IRQ Card A Pin R.E. Detected */ 
#define PER_CA_ERDY_F 0x00100000   /* Enable for RDY/IRQ Card A Pin F.E. Detected */ 
#define RESERVED40    0x000F0000
#define PER_CB_EVS1   0x00008000   /* Enable Volt Sense 1 Card B Changed */
#define PER_CB_EVS2   0x00004000   /* Enable Volt Sense 2 Card B Changed */
#define PER_CB_EWP    0x00002000   /* Enable for Write Protect for Card B Changed */
#define PER_CB_ECD2   0x00001000   /* Enable for Card Detect 2 for Card B Changed */
#define PER_CB_ECD1   0x00000800   /* Enable for Card Detect 1 for Card B Changed */
#define PER_CB_EBVD2  0x00000400   /* Enable Batt Volt/SPKR in for Card B Changed */
#define PER_CB_EBVD1  0x00000200   /* Enable for Batt Volt/STSCHG in for Card B Changed */
#define RESERVED41    0x00000100   
#define CB_ERDY_L     0x00000080   /* Enable for RDY/IRQ of Card B Pin is Low */
#define CB_ERDY_H     0x00000040   /* Enable for RDY/IRQ of Card B Pin is High */
#define CB_ERDY_R     0x00000020   /* Enable for RDY/IRQ Card B Pin R.E. Detected */
#define CB_ERDY_F     0x00000010   /* Enable for RDY/IRQ Card B Pin F.E. Detected */
#define RESERVED42    0x0000000F  



/*                                    MEMC           */
/* Memory Command Register (MCR) */
#define MCR_OP        0xC0000000   /* Command Opcode */
#define RESERVED59    0x3F000000   
#define MCR_UM        0x00800000   /* User Machine */
#define RESERVED60    0x007F0000   
#define MCR_MB        0x0000E000   /* Memory Bank */
#define RESERVED61    0x00001000   
#define MCR_MCLF      0x00000F00   /* Memory Command Loop Field */
#define RESERVED62    0x000000C0   
#define MCR_MAD       0x0000003F   /* Machine Address */



/* Machine A Mode Register (MAMR) */
#define MAMR_PTA         0xFF000000   /* Periodic Timer A Period */
#define MAMR_PTAE        0x00800000   /* Periodic Timer A Enable */
#define MAMR_AMA         0x00700000   /* Address Multiplex Size A */
#define RESERVED63       0x00080000