d860_ini.c

基于vxworks操作系统的电话语音平台系统

/************************************************************************/
/*                                                              		*/
/*                                                              		*/
/* (C) Copyright Bangyan Information Technology Ltd, 2000/9.            */
/*  All right reserved                                          		*/
/*                                                              		*/
/* Author: Zhuguosheng 	                                  				*/
/*                                                              		*/
/* Description:                                                 		*/
/*     Driver Set - CPM initiating specific routines.            		*/
/*                                                              		*/
/* Routines                                                     		*/
/*                                                                      */
/************************************************************************/
#include "PUB\PUB_INCL.H"
#include "DRVS\DRV860\PUB\NETCOMM.H"      /* global defines */
#include "DRVS\DRV860\PUB\D860_PUB.H"
#include "DRVS\DRV860\PUB\mpc860.h"       /* IMMR definitions and declarations */
#include "DRVS\DRV860\PUB\masks860.h"     /* Global masks header file */
#include "DRVS\DRV860\UART\SCC_UART.H"



extern BOOL DrvQmcInitiate( VOID );
extern BOOL DrvFecInitiate( VOID );
extern BOOL DrvUartInitiate( VOID );
extern VOID ResetRisc(VOID);
STATIC VOID MpcMemAddrInit(VOID);

EPPC *quicc;
SCC_TABLE scc_table;
UC Mpc860InitCompFlag=0;

VOID MpcMemAddrInit(VOID)
{
	/* CS1 defined as IO_SPACE AND TIMER at 0x40000000 */
	quicc->memc_or1 = 0xF8000970;			/*0xffe00970;*/
	quicc->memc_br1 = 0x40000401;

	/* CS3 not used 
	quicc->memc_or3 = 0xff000934;
	quicc->memc_br3 = 0x10000000;*/

	/* CS4 defined as Flash or SRAM at 0x30000000 */
	quicc->memc_or4 = 0xff000934;
	quicc->memc_br4 = 0x20000001;

	/* CS5 defined as DSP Hpi Space at 0x50000000 */
	quicc->memc_or5 = 0xffe00924;
	quicc->memc_br5 = 0x50000801;

	/*	CS6 RESERVED */
	quicc->memc_or6 = 0xff000934;
	quicc->memc_br6 = 0x80000000;

	/* CS7 defined as FPGA switch Internal Register Space at 0x60000000 */
	quicc->memc_or7 = 0xff000940;
	quicc->memc_br7 = 0x60000801;
}


VOID QuiccInit(VOID)
{
	SI i,j;
	/*
	 * Set the address of the quicc start address (MBAR)
	 */
#ifdef _NUCLEUS_RTOS
	quicc = (EPPC *)QUICC_ADDRESS;
#endif

#ifdef _VXWORKS_RTOS
	quicc = (EPPC *)(vxImmrGet());
#endif

	for (j=0; j<NUM_OF_SCCS; j++)
		scc_table[j].init_flag = 0;
}

VOID scc_init(UI scc_number, UI number_of_rx_buf, UI number_of_tx_buf)
{
	if( scc_number < NUM_OF_SCCS )
	{
		scc_table[scc_number].no_of_rcv_bd = number_of_rx_buf;
		scc_table[scc_number].no_of_trn_bd = number_of_tx_buf;
		scc_table[scc_number].init_flag    = 1;
	}
}

extern VOID EnableSystemBus(VOID);

VOID MPC860_Initiate( VOID )
{
/*	QuiccInit();*/

	MpcMemAddrInit();

	EnableSystemBus();

	DrvQmcInitiate();

#ifdef _NUCLEUS_RTOS
	DrvFecInitiate();
	/* DrvUartInitiate(); */   /* dont start Uart */	
#endif

#ifdef _NUCLEUS_RTOS
	EnableMpc860Interrupt();
#endif

	Mpc860InitCompFlag=1;
}