qmc.h

基于vxworks操作系统的电话语音平台系统

#ifndef __QMC_H
#define __QMC_H

#define NUM_OF_HTB_CHAN	  2

#define NUM_OF_CHANNELS   (48+NUM_OF_HTB_CHAN)

#define NUM_OF_TIME_SLOTS 64
#define MAX_SLOT_NUM      64

/* define the serial clock for the multi channel */
#define CHANNEL_RATE    (64*1024)
#define TDM_RATE        (CHANNEL_RATE * NUM_OF_TIME_SLOTS)
#define SYNC_RATE       (NUM_OF_TIME_SLOTS * 8)


/*
 * transmit BD's
 */
#define T_R     0x8000          /* ready bit */
#define T_W     0x2000          /* wrap bit */
#define T_I     0x1000          /* interrupt on completion */
#define T_L     0x0800          /* last in frame */
#define T_TC    0x0400          /* transmit CRC (when last) */
#define T_CM    0x0200          /* continuous mode */
#define HDLC_QMC_T_PAD   0x000f          /* pad seq */

/*
 * hdlc interrupts and mask
 */
#define HDLC_NID        0x2000  /* Not Idle */
#define HDLC_IDL        0x1000  /* IDLE sequence status changed */
#define HDLC_MRF        0x0020  /* max.rec.frame violation */
#define HDLC_UN         0x0010  /* Underrun */
#define HDLC_RXF        0x0008  /* receive frame */
#define HDLC_BSY        0x0004  /* busy condition */
#define HDLC_TXB        0x0002  /* transmit buffer */
#define HDLC_RXB        0x0001  /* receive buffer */


/*
 * receive BD's
 */
#define R_E     0x8000          /* buffer empty */
#define R_W     0x2000          /* wrap bit */
#define R_I     0x1000          /* interrupt on reception */
#define R_L     0x0800          /* last BD in frame */
#define R_F     0x0400          /* first BD in frame */
#define R_CM    0x0200          /* continuous mode */

#define R_LG    0x0020          /* frame too long */
#define R_NO    0x0010          /* non-octet aligned */
#define R_AB    0x0008          /* received abort sequence */
#define R_CR    0x0004          /* receive CRC error */
#define HDLC_QMC_R_ERROR ( R_LG | R_NO | R_CR | R_AB)


#define C_MASK_CCITT16 0x0000F0B8
#define C_MASK_CCITT32 0xDEBB20E3
#define C_PRES_CCITT16 0x0000FFFF
#define C_PRES_CCITT32 0xFFFFFFFF

#define HDLC_CHAN_MODE  0x8000

#define HDLC_ZD_STATE   0x00000080
#define HDLC_ZI_STATE   0x00000100
#define TRANS_ZD_STATE  0x18000080
#define TRANS_ZI_STATE  0x00000100

/*
 * HDLC CHAMR (Channel Mode register)
 */
#define HDLC_CHAMR_MODE         0x8000  /* Select HDLC or Transparant mode */
#define HDLC_CHAMR_RD           0x4000  /* Reverse bit order ( transparant ) */
#define HDLC_CHAMR_IDLM         0x2000  /* Idle mode */
#define HDLC_CHAMR_ENT          0x1000  /* Enable Transmit*/
#define HDLC_CHAMR_POL          0x0100  /* Enable Polling */

#define HDLC_CHAMR_CRC          0x0080  /* Select CCITT 32 bit/16 bit CRC */
#define HDLC_CHAMR_NOF          0x000f  /* number of flags before frame */


#define QMC_STATE       0x8000


#define MRBLR_T         600
#define CRC_LEN         2
#define RECEIVE_INTR    1
#define INTR_MEM_SPACE  4096
#define NUMBER_OF_RX_BUF 128
#define NUMBER_OF_TX_BUF 128
#define MAX_NUM_OF_BDS   ((NUMBER_OF_TX_BUF+NUMBER_OF_RX_BUF)*NUM_OF_CHANNELS)





/* Setup structure for the multichannel SCC */
typedef struct Multi_Chan_Pram_Setup {
	unsigned long 	mcbase;	        /* bds table base address */
	unsigned long	bds_tbl_size; 	/* bds table size ( allocated by the user)*/
	short			mrblr;		/* Max. receive buffer length */
	short			grfthr;		/* Global receive frame threshold*/
	unsigned short	*intbase;	/* interrupt table address*/
	short			inter_tbl_size;	/* interrupt table size ( allocated by the user) */
	short			rx_max_time_slot;/* Max time slot to support RX */
	short			tx_max_time_slot;/* Max time slot to support TX */
} MULTI_CHAN_SETUP;

typedef struct _QMC_TABLE
{
	short                       init_flag;
	short					   scc_number;
	QUICC_BD                  *tbd;     /* Pointer to next Transmit BD  */
	QUICC_BD                  *NextFreeTbd;     /* Pointer to next Transmit BD  */

	short					   tbd_len;  /* Number of Transmit BD's
										   currently in transmission    */
	QUICC_BD                  *rbd;     /* Pointer to next Receive BD   */
	short					   no_of_rcv_bd;
	short					   no_of_trn_bd;
	short					   max_frame_length;
	unsigned char             continuous_rx;
	unsigned char             continuous_tx;

	QUICC_BD                  *FirstTxBd, *FirstRxBd;
} QMC_TABLE[NUM_OF_CHANNELS];


typedef struct _QUICC_32_MANAGER
{
	/* Current interrupt to handle by sw */
	unsigned short       *CurrIntr[NUM_OF_SCCS];
	short				 num_of_bds[NUM_OF_SCCS];
	short				 allocated_bds[NUM_OF_SCCS];

	UL mcbase;
} QUICC_32_MANAGER;

typedef struct _HDLC_QMC_SPECIFIC
{
	/* parameter ram */
	CRC    								crc;
	unsigned char                       number_of_flags;
	unsigned char                       idle_mode;
	unsigned char                       reverse_mode;
	unsigned short                      intmask;
	unsigned short                      max_frame_length;
	enum { TRANSPARENT_32, HDLC_32 }    mode;
	unsigned char                       continuous_rx;
	unsigned char                       continuous_tx;
} HDLC_QMC_SPECIFIC;


/*
 * User callable routines prototypes (hdlc specific)
 */
void qmc_scc_init(short scc_num,short first_log_chan,MULTI_CHAN_SETUP *setup);
void print_qmc_rbd(short channel_num);
void print_qmc_tbd(short channel_num);

#endif



extern  UL  QmcShortPacketNum[];
extern  UL  QmcCrcErrorNum[];