📄 fec_init.c
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/************************************************************************/
/* */
/* */
/* (C) Copyright Bangyan Information Technology Ltd, 2000/9. */
/* All right reserved */
/* */
/* Author: Zhuguosheng */
/* */
/* Description: */
/* Driver Set - SCC FEC initiating specific routines. */
/* */
/* Routines */
/* Delay */
/* FecInit */
/* FecTxRxBDInit */
/* StartFec */
/* InitFec */
/* */
/************************************************************************/
#include "PUB\PUB_INCL.H"
#include "DRVs\DRV860\PUB\NETCOMM.H" /* global defines */
#include "DRVs\DRV860\PUB\D860_PUB.H"
#include "DRVs\DRV860\PUB\MPC860.H" /* IMMR definitions and declarations */
#include "DRVs\DRV860\PUB\MASKS860.h" /* Global masks header file */
#include "FEC.H"
extern EPPC *quicc;
STATIC VOID Delay(UWORD num);
STATIC VOID InitMII( VOID );
STATIC VOID FecTxRxBDInit( VOID );
VOID StartFec( VOID );
VOID FecInit( VOID );
QUICC_BD FecRxBd[MAX_FEC_RX_BDS], FecTxBd[MAX_FEC_TX_BDS];
UI CurFecRxBd=0,CurFecTxBd=0;
STATIC VOID Dummy( VOID )
{
UC i=0;
i++;
}
STATIC VOID Delay(UL num)
{
while(num--)
{
Dummy();
}
}
STATIC VOID InitMII_verB( VOID )
{
quicc->t_ecntrl = T_ECNTRL_ETHERNETRESET; /* Put the FEC in reset state */
Delay(10000);
quicc->t_imask = T_IEVENT_RECEIVEFRAMEINT|T_IEVENT_TRANSMITFRAMEINT;
quicc->t_ievent = 0x00000000;
quicc->t_ivec = ( FEC_LEVEL << T_IVEC_LEVEL ); /* Set intrpt level */
quicc->t_addr_low = STATION_ADDR_LOW; /* First four bytes of address */
quicc->t_addr_high = STATION_ADDR_HIGH; /* Last two bytes of address */
quicc->t_hash_table_high = 0;
quicc->t_hash_table_low = 0;
quicc->t_r_buff_size = RX_BUFFER_SIZE;
/*-----------------------------------------------*/
/* Configure start of Rx and Tx BD rings */
/*-----------------------------------------------*/
quicc->t_r_des_start = (UL) &FecRxBd[0];
quicc->t_x_des_start = (UL) &FecTxBd[0];
/*-----------------------------------------------*/
/* Configure FEC receiver mode: */
/* Not promiscuous, MII interface, */
/* full duplex (i.e. DRT not set), loopback */
/*-----------------------------------------------*/
#ifdef FEC_INTERNAL_LOOPBACK
quicc->t_r_cntrl = (MIIMODE|PROMISCUOUS|INTERNALLOOPBACK);
#else
quicc->t_r_cntrl = (MIIMODE|PROMISCUOUS);
#endif
quicc->t_x_cntrl = FULLDUPLEXENABLE;
quicc->t_fun_code = 0x78000000;
quicc->t_mii_speed = (0xC <<T_MII_SPEED_MSPD);
quicc->t_r_hash = (0x000005F2); /* 1522--allows for VLAN tags, no affect*/
/* Configure Port D pins to enable MII interface */
quicc->pio_pdpar = 0x1FFF;
quicc->pio_pddir = 0x1C58;
}
STATIC VOID InitMII_verD( VOID )
{
quicc->t_ecntrl = T_ECNTRL_ETHERNETRESET; /* Put the FEC in reset state */
Delay(10000);
quicc->t_imask = T_IEVENT_RECEIVEFRAMEINT|T_IEVENT_TRANSMITFRAMEINT;
quicc->t_ievent = 0x00000000;
quicc->t_ivec = ( FEC_LEVEL << T_IVEC_LEVEL ); /* Set intrpt level */
quicc->t_wmrk = 0x00000003; /* special for D */
quicc->t_addr_low = STATION_ADDR_LOW; /* First four bytes of address */
quicc->t_addr_high = STATION_ADDR_HIGH; /* Last two bytes of address */
quicc->t_hash_table_high = 0;
quicc->t_hash_table_low = 0;
quicc->t_r_buff_size = RX_BUFFER_SIZE;
/*-----------------------------------------------*/
/* Configure start of Rx and Tx BD rings */
/*-----------------------------------------------*/
quicc->t_r_des_start = (UL) &FecRxBd[0];
quicc->t_x_des_start = (UL) &FecTxBd[0];
/*-----------------------------------------------*/
/* Configure FEC receiver mode: */
/* Not promiscuous, MII interface, */
/* full duplex (i.e. DRT not set), loopback */
/*-----------------------------------------------*/
#ifdef FEC_INTERNAL_LOOPBACK
quicc->t_r_cntrl = (MIIMODE|PROMISCUOUS|INTERNALLOOPBACK);
#else
quicc->t_r_cntrl = (MIIMODE|PROMISCUOUS);
#endif
quicc->t_x_cntrl = FULLDUPLEXENABLE;
quicc->t_fun_code = 0x78000000;
quicc->t_mii_speed = (0xC <<T_MII_SPEED_MSPD);
quicc->t_r_hash = (0x000005F2); /* 1522--allows for VLAN tags, no affect*/
/*Configure Port D pins to enable MII interface, special for verD */
quicc->pio_pdpar = 0x1FFF;
quicc->pio_pddir = 0x1FFF;
}
STATIC VOID FecTxRxBDInit( VOID )
{
UI i;
quicc->t_ecntrl = T_ECNTRL_ETHERNETRESET; /* Put the FEC in reset state */
/* Set FEC RecvBDs */
for( i=0; i<MAX_FEC_RX_BDS; i++ )
{
FecRxBd[i].status = RX_BD_E;
FecRxBd[i].length = 0;
FecRxBd[i].buf = (UC*)BYMalloc(RX_BUFFER_SIZE+FEC_CRC_LEN);
}
FecRxBd[MAX_FEC_RX_BDS-1].status |=RX_BD_W;
/* Set FEC SendBDs */
for( i=0; i<MAX_FEC_TX_BDS; i++ )
{
FecTxBd[i].status = 0;
FecTxBd[i].length = 0;
FecTxBd[i].buf = (UC*)BYMalloc(TX_BUFFER_SIZE);
}
FecTxBd[MAX_FEC_TX_BDS-1].status |= TX_BD_W;
}
STATIC VOID StartFec_verB( VOID )
{
quicc->t_ecntrl = T_ECNTRL_ETHERNETENABLE;
quicc->t_r_des_active = FEC_BD_ACTIVE;
quicc->t_x_des_active = FEC_BD_ACTIVE;
}
STATIC VOID StartFec_verD( VOID )
{
quicc->t_ecntrl = (T_ECNTRL_ETHERNETENABLE|T_ECNTRL_ETHERNETPINMUX);
quicc->t_r_des_active = FEC_BD_ACTIVE;
quicc->t_x_des_active = FEC_BD_ACTIVE;
}
VOID StartFec( VOID )
{
#ifdef MPC860T_VERSION_B
StartFec_verB( );
#endif
#ifdef MPC860T_VERSION_D
StartFec_verD( );
#endif
}
VOID FecInterruptInit(VOID)
{
}
STATIC VOID InitMII( VOID )
{
#ifdef MPC860T_VERSION_B
InitMII_verB( );
#endif
#ifdef MPC860T_VERSION_D
InitMII_verD( );
#endif
}
VOID FecInit( VOID )
{
FecInterruptInit();
FecTxRxBDInit();
InitMII();
}
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