fec.h

基于vxworks操作系统的电话语音平台系统

#ifndef __FEC_H
#define __FEC_H

/* Ethernet Control register, bit definitions */
#define	T_ECNTRL_ETHERNETENABLE		0x02
#define	T_ECNTRL_ETHERNETRESET		0x01
#define	T_ECNTRL_ETHERNETPINMUX     0X04


/* Interrupt Event register, bit definitions */
/*   also good for interrupt mask register  */
#define	T_IEVENT_HEARTBEATERROR    0x80000000
#define	T_IEVENT_BABBLINGRECEIVER  0x40000000
#define	T_IEVENT_BABBLINGTRANSMIT  0x20000000
#define	T_IEVENT_GRACEFULSTOPACK   0x10000000
#define	T_IEVENT_TRANSMITFRAMEINT  0x08000000
#define	T_IEVENT_TRANSMITBUFINT    0x04000000
#define	T_IEVENT_RECEIVEFRAMEINT   0x02000000
#define	T_IEVENT_RECEIVEBUFINT     0x01000000
#define	T_IEVENT_MIIINT            0x00800000
#define	T_IEVENT_ETHERNETBUSERROR	0x00400000

/* Ivec */
#define	T_IVEC_NONE                0
#define	T_IVEC_NONTIMECRITICAL     1
#define	T_IVEC_TRANSMITINT         2
#define	T_IVEC_RECEIVEINT          3
#define	T_IVEC_LEVEL               29          /* rotate offset */

/* Receive or Transmit Buffer Descriptor active */
#define	FEC_BD_ACTIVE                  0x01000000

/* Mii data */
#define	T_MII_DATA_ST              0x40000000
#define	T_MII_DATA_READ            0x20000000
#define	T_MII_DATA_WRITE           0x10000000
#define	T_MII_DATA_PHYADDRESS      23          /* rotate offset */
#define	T_MII_DATA_REGADDRESS      18          /* rotate offset */
#define	T_MII_DATA_TA              0x00020000

/* Mii Speed */
#define	T_MII_SPEED_MSPD           1		      /* rotate offset */
#define	T_MII_SPEED_DISPREAMBLE		0x00000008

/* DMA Function Code */
#define	DATABO0                    0x40000000
#define	DATABO1                    0x20000000
#define	DESCBO0                    0x10000000
#define	DESCBO1                    0x08000000
#define	FC1                        0x04000000
#define	FC2                        0x02000000
#define	FC3                        0x01000000

/* Receive Control */
#define	PROMISCUOUS                0x00000008
#define	MIIMODE                    0x00000004
#define	RDT                        0x00000002
#define	INTERNALLOOPBACK           0x00000001
#define BROADCASTREJECT            0X00000010

/* Transmit Control */
#define	FULLDUPLEXENABLE           0x00000004
#define	HEARTBEATCONTROL           0x00000002
#define	GRACEFULTRANSMITSTOP       0x00000001

/*****************************************************************
			Ethernet Receive/Transmit Buffer Descriptor
*****************************************************************/

#define RX_BD_E      0x8000
#define RX_BD_RES    0x4000
#define RX_BD_W      0x2000
#define RX_BD_L      0x0800
#define RX_BD_F      0x0400
#define RX_BD_RES1   0x0200
#define RX_BD_M      0x0100
#define RX_BD_RES2   0x00c0
#define RX_BD_BC	 0x0080		/*Added by Zhuguosheng*/
#define RX_BD_MC     0x0040     /*Added by Zhuguosheng*/
#define RX_BD_LG     0x0020
#define RX_BD_NO     0x0010
#define RX_BD_SH     0x0008
#define RX_BD_CR     0x0004
#define RX_BD_OV     0x0002
#define RX_BD_TR     0x0001


#define TX_BD_R      0x8000
#define TX_BD_RES    0x4000
#define TX_BD_W      0x2000
#define TX_BD_L      0x0800
#define TX_BD_TC     0x0400
#define TX_BD_DEF    0x0200
#define TX_BD_HB     0x0100
#define TX_BD_LC     0x0080
#define TX_BD_RL     0x0040
#define TX_BD_RC     0x003c
#define TX_BD_UN     0x0002
#define TX_BD_CSL    0x0001

#define STATION_ADDR_LOW  0x66554433   /* First four bytes of Ethernet addr */
#define STATION_ADDR_HIGH 0x22110000   /* Last two bytes of Ethernet addr   */
									   /* extended with 0x0000              */
#define FEC_CRC_LEN    4
#define RX_BUFFER_SIZE 1520 /* Must be divisible by 16.  For this example,  */
							/* we select a size which can fit a maximum-    */
							/* length Ethernet frame (1518).                */

#define TX_BUFFER_SIZE 1514 /* For our example, we choose a maximum-length  */
							/* Ethernet frame.  The FEC will add 4 bytes of */
							/* CRC-32 on the end, making it 1518 in total.  */
							/* This value is changeable, but this example   */
							/* assumes and requires that                    */
							/*     RX_BUFFER_SIZE >= (TX_BUFFER_SIZE+4)     */
#define FEC_LEVEL 5 	/* integer between 0 and 7 inclusive */
#define MAX_FEC_TX_BDS  64
#define MAX_FEC_RX_BDS  64

#define VECTOR_BLOCK_LEN 0x100
#define BASE_EVT 0x0  /* Base Address of Exception Vector Table */
#define EXT_INT_VECTOR ((BASE_EVT) + 0x500)  /* Base address of external */
#define NEXT_VECTOR (EXT_INT_VECTOR + 0x100)


#endif