📄 uart_ini.c
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/************************************************************************/
/* */
/* */
/* (C) Copyright Bangyan Information Technology Ltd, 2000/9. */
/* All right reserved */
/* */
/* Author: Zhuguosheng */
/* */
/* Description: */
/* Driver Set - SCC UART initiating specific routines. */
/* */
/* Routines */
/* */
/************************************************************************/
#ifdef _NUCLEUS_RTOS
#include "RTOS\NUCLEUS\TASK\TASK_NUC.H"
#endif
#include "PUB\PUB_INCL.H"
#include "DRVS\DRV860\PUB\NETCOMM.H" /* global defines */
#include "DRVS\DRV860\PUB\D860_PUB.H"
#include "DRVS\DRV860\PUB\MPC860.H" /* IMMR definitions and declarations */
#include "DRVS\DRV860\PUB\MASKS860.h" /* Global masks header file */
#include "DRVS\DRV860\UART\SCC_UART.H"
extern EPPC *quicc;
extern SCC_TABLE scc_table;
extern VOID uart_interrupt(UI scc_num);
extern VOID issue_cmd(UI cmd, SI scc_num);
CONT_CHAR cc_saved[NUM_OF_SCCS][CC_MAX];
SI number_of_cc_saved[NUM_OF_SCCS];
VOID uart_init(SI scc_num, UART_SPECIFIC *uart_spec)
{
QUICC_BD *rbd;
QUICC_BD *tbd;
struct uart_pram *uart_pram;
struct scc_regs *regs;
SI i;
UI base;
UL divider;
/* scc_num must be valid and initialized. */
if (scc_num < 0 || scc_num >= NUM_OF_SCCS ||
!scc_table[scc_num].init_flag)
return;
/*
* INITIALIZE INTERNAL SCC STRUCTURE
* ---------------------------------
*/
scc_table[scc_num].inter_ptr = uart_interrupt;
scc_table[scc_num].max_frame_length = uart_spec->max_frame_length;
/*
* INITIALIZE SCC COMMON PROTOCOL PARAMATER RAM
*/
/* Pointer to corresponding uart parameter ram */
uart_pram = &quicc->PRAM[scc_num].pg.scc.u;
/* Free space in buffer descriptions area. */
base = BD_BASE;
for (i=0; i<scc_num; i++)
if (scc_table[i].init_flag)
base += scc_table[i].no_of_rcv_bd + scc_table[i].no_of_trn_bd;
/*
* Initialize Rx BD ring:
* clear all BD`s status field and set R_W on last BD
*/
uart_pram->rbase = base * sizeof(struct quicc_bd);
scc_table[scc_num].rbd = rbd = RBD_ADDR(quicc,uart_pram);
for (i = 0; i <scc_table[scc_num].no_of_rcv_bd; i++)
{
rbd->length = 0;
if((rbd->buf=BYMalloc(uart_spec->max_frame_length))!=NULL)
rbd->status = R_E | R_I;
else
rbd->status = 0;
rbd++;
}
--rbd;
rbd->status |= R_W;
/*
* Initialize Tx BD ring:
* clear all BD`s status field and set T_W on last BD
*/
uart_pram->tbase = (base + scc_table[scc_num].no_of_rcv_bd) \
* sizeof(struct quicc_bd);
tbd = TBD_ADDR(quicc,uart_pram);
scc_table[scc_num].tbd_get = tbd;
scc_table[scc_num].tbd_put = tbd;
for (i = 0; i <scc_table[scc_num].no_of_trn_bd ; i++)
{
tbd->status = 0;
tbd->length = 0;
tbd->buf = BYMalloc(uart_spec->max_frame_length);
tbd++;
}
--tbd;
tbd->status |= T_W;
uart_pram->rfcr = RFCR;
uart_pram->tfcr = TFCR;
uart_pram->mrblr = uart_spec->max_frame_length;
/*
* INITIALIZE UART SPECIFIC PROTOCOL PARAMATER RAM
* ---------------------------------------------------
*/
uart_pram->max_idl = 3;
uart_pram->brkcr = 3;
uart_pram->parec = 0;
uart_pram->frmec = 0;
uart_pram->nosec = 0;
uart_pram->brkec = 0;
for (i=0; i<8; i++)
uart_pram->cc[0] = UART_LAST_CHAR;
for (i=0; i<uart_spec->number_of_cc; i++)
{
cc_saved[scc_num][i].reject = uart_spec->cc[i].reject;
cc_saved[scc_num][i].ch = uart_spec->cc[i].ch;
cc_saved[scc_num][i].user_func = uart_spec->cc[i].user_func;
uart_pram->cc[i] = uart_spec->cc[i].ch & 0xFF;
if (uart_spec->cc[i].reject)
uart_pram->cc[i] |= UART_REJECT_CHAR;
}
uart_pram->cc[7] |= UART_LAST_CHAR;
uart_pram->rccm = UART_RCCM;
number_of_cc_saved[scc_num] = uart_spec->number_of_cc;
/*
* INITIALIZE SCC REGISTERS AREA
* -----------------------------
*/
/* Pointer to SCC registers area */
regs = &quicc->scc_regs[scc_num];
/*
* mask all the events
*/
regs->scc_sccm = UART_GLr | UART_GLt | UART_AB | UART_IDL |UART_GRA |
UART_BRKe | UART_BRKs | UART_CCR | UART_BSY | UART_TX | UART_RX;
//Set CLOCK_RATE_16 and MODE_UART;
regs->scc_gsmr_h = 0x00000020;
regs->scc_gsmr_l = 0x00028004;
/* protocol specific mode register */
regs->scc_psmr = UART_PSMR_UM_NORM;
switch (uart_spec->stop)
{
case 1:
break;
case 2:
regs->scc_psmr |= UART_PSMR_SL;
break;
}
switch (uart_spec->data)
{
case 5:
regs->scc_psmr |= UART_PSMR_CL5;
break;
case 6:
regs->scc_psmr |= UART_PSMR_CL6;
break;
case 7:
regs->scc_psmr |= UART_PSMR_CL7;
break;
case 8:
regs->scc_psmr |= UART_PSMR_CL8;
break;
}
switch (uart_spec->parity)
{
case PARITY_NO:
break;
case PARITY_ODD:
regs->scc_psmr |= UART_PSMR_PEN | UART_PSMR_RPM_ODD | UART_PSMR_TPM_ODD;
break;
case PARITY_LOW:
regs->scc_psmr |= UART_PSMR_PEN | UART_PSMR_RPM_LOW | UART_PSMR_TPM_LOW;
break;
case PARITY_EVEN:
regs->scc_psmr |= UART_PSMR_PEN | UART_PSMR_RPM_EVEN | UART_PSMR_TPM_EVEN;
break;
case PARITY_HIGH:
regs->scc_psmr |= UART_PSMR_PEN | UART_PSMR_RPM_HIGH | UART_PSMR_TPM_HIGH;
break;
}
/*
* Clock setting
*/
//zhu : disable the flowing
/*
quicc->brgc[scc_num].l = 0L;
divider = SYSTEM_CLOCK/(uart_spec->baud*16);
if( divider > MAX_DIV )
{
quicc->brgc[scc_num].b.div16 = 1;
quicc->brgc[scc_num].b.cd = divider/16;
}
else
{
quicc->brgc[scc_num].b.cd = divider;
}
quicc->brgc[scc_num].b.en = 1;
*/
quicc->brgc1 = 0x010144;
/*
* Initialize RBPTR TBPTR (issue INIT_RXTX_PARAMS) commands
*/
issue_cmd(INIT_RXTX_PARAMS ,scc_num );
}
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