📄 modulation.mdl

📁 利用matlab/simulink仿真了CDMA2
💻 MDL
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Library {
  Name			  "modulation"
  Version		  5.0
  SaveDefaultBlockParams  on
  LibraryLinkDisplay	  "none"
  ShowLoopsOnError	  on
  IgnoreBidirectionalLines off
  CovSaveName		  "covdata"
  CovMetricSettings	  "dw"
  CovNameIncrementing	  off
  CovHtmlReporting	  on
  covSaveCumulativeToWorkspaceVar on
  CovSaveSingleToWorkspaceVar on
  CovCumulativeReport	  off
  BlockNameDataTip	  off
  BlockParametersDataTip  off
  BlockDescriptionStringDataTip	off
  ToolBar		  on
  StatusBar		  on
  BrowserShowLibraryLinks on
  BrowserLookUnderMasks	  off
  Created		  "Fri Nov 11 10:57:00 2005"
  UpdateHistory		  "UpdateHistoryNever"
  ModifiedByFormat	  "%<Auto>"
  LastModifiedBy	  "user"
  ModifiedDateFormat	  "%<Auto>"
  LastModifiedDate	  "Mon Nov 28 15:49:42 2005"
  ModelVersionFormat	  "1.%<AutoIncrement:3>"
  ConfigurationManager	  "None"
  SimParamPage		  "Solver"
  LinearizationMsg	  "none"
  Profile		  off
  ParamWorkspaceSource	  "MATLABWorkspace"
  ExtModeMexFile	  "ext_comm"
  ExtModeBatchMode	  off
  ExtModeTrigType	  "manual"
  ExtModeTrigMode	  "normal"
  ExtModeTrigPort	  "1"
  ExtModeTrigElement	  "any"
  ExtModeTrigDuration	  1000
  ExtModeTrigHoldOff	  0
  ExtModeTrigDelay	  0
  ExtModeTrigDirection	  "rising"
  ExtModeTrigLevel	  0
  ExtModeArchiveMode	  "off"
  ExtModeAutoIncOneShot	  off
  ExtModeIncDirWhenArm	  off
  ExtModeAddSuffixToVar	  off
  ExtModeWriteAllDataToWs off
  ExtModeArmWhenConnect	  on
  ExtModeSkipDownloadWhenConnect off
  ExtModeLogAll		  on
  ExtModeAutoUpdateStatusClock on
  SimulationMode	  "normal"
  ConsistencyChecking	  "none"
  ArrayBoundsChecking	  "none"
  AlgebraicLoopMsg	  "warning"
  BlockPriorityViolationMsg "warning"
  MinStepSizeMsg	  "warning"
  InheritedTsInSrcMsg	  "warning"
  DiscreteInheritContinuousMsg "warning"
  MultiTaskRateTransMsg	  "error"
  SingleTaskRateTransMsg  "none"
  CheckForMatrixSingularity "none"
  IntegerOverflowMsg	  "warning"
  Int32ToFloatConvMsg	  "warning"
  ParameterDowncastMsg	  "error"
  ParameterOverflowMsg	  "error"
  ParameterPrecisionLossMsg "warning"
  UnderSpecifiedDataTypeMsg "none"
  UnnecessaryDatatypeConvMsg "none"
  VectorMatrixConversionMsg "none"
  InvalidFcnCallConnMsg	  "error"
  SignalLabelMismatchMsg  "none"
  UnconnectedInputMsg	  "warning"
  UnconnectedOutputMsg	  "warning"
  UnconnectedLineMsg	  "warning"
  SfunCompatibilityCheckMsg "none"
  ProdHWDeviceType	  "Microprocessor"
  ProdHWWordLengths	  "8,16,32,32"
  RTWMakeCommand	  "make_rtw"
  RTWGenerateCodeOnly	  off
  RTWRetainRTWFile	  off
  TLCProfiler		  off
  TLCDebug		  off
  TLCCoverage		  off
  TLCAssertion		  off
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Inport
      Port		      "1"
      PortDimensions	      "-1"
      SampleTime	      "-1"
      ShowAdditionalParam     off
      LatchInput	      off
      DataType		      "auto"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      SignalType	      "auto"
      SamplingMode	      "auto"
      Interpolate	      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      Product
      Inputs		      "2"
      Multiplication	      "Element-wise(.*)"
      ShowAdditionalParam     off
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
    }
    Block {
      BlockType		      RealImagToComplex
      Input		      "Real and imag"
      ConstantPart	      "0"
    }
    Block {
      BlockType		      Reference
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      PortCounts	      "[]"
      SFunctionModules	      "''"
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      on
      Permissions	      "ReadWrite"
      RTWSystemCode	      "Auto"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      Sum
      IconShape		      "rectangular"
      Inputs		      "++"
      ShowAdditionalParam     off
      InputSameDT	      on
      OutDataTypeMode	      "Same as first input"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      LockScale		      off
      RndMeth		      "Floor"
      SaturateOnIntegerOverflow	on
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "modulation"
    Location		    [2, 82, 1014, 718]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Inport
      Name		      "SCH2"
      Position		      [215, 153, 245, 167]
    }
    Block {
      BlockType		      Inport
      Name		      "PCH"
      Position		      [205, 188, 235, 202]
      Port		      "2"
    }
    Block {
      BlockType		      Inport
      Name		      "DCCH"
      Position		      [205, 223, 235, 237]
      Port		      "3"
    }
    Block {
      BlockType		      Inport
      Name		      "FCH"
      Position		      [205, 258, 235, 272]
      Port		      "4"
    }
    Block {
      BlockType		      Inport
      Name		      "SCH1/CCCH/EACH"
      Position		      [210, 293, 240, 307]
      Port		      "5"
    }
    Block {
      BlockType		      Inport
      Name		      "In6"
      Position		      [205, 328, 235, 342]
      Port		      "6"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Subsystem1"
      Ports		      [6, 1]
      Position		      [325, 139, 490, 356]
      TreatAsAtomicUnit	      off
      MaskInitialization      "MS_Modulation_Initialization"
      MaskDisplay	      "disp('Modulation\\n\\n(cdma 2000 MS)')"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      System {
	Name			"Subsystem1"
	Location		[2, 82, 1014, 718]
	Open			on
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"A4"
	PaperUnits		"centimeters"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "SCH2"
	  Position		  [60, 133, 90, 147]
	}
	Block {
	  BlockType		  Inport
	  Name			  "PCH"
	  Position		  [60, 163, 90, 177]
	  Port			  "2"
	}
	Block {
	  BlockType		  Inport
	  Name			  "DCCH"
	  Position		  [60, 193, 90, 207]
	  Port			  "3"
	}
	Block {
	  BlockType		  Inport
	  Name			  "FCH"
	  Position		  [60, 268, 90, 282]
	  Port			  "4"
	}
	Block {
	  BlockType		  Inport
	  Name			  "SCH1/CCCH/EACH"
	  Position		  [60, 298, 90, 312]
	  Port			  "5"
	}
	Block {
	  BlockType		  Inport
	  Name			  "In6"
	  Position		  [705, 333, 735, 347]
	  Port			  "6"
	}
	Block {
	  BlockType		  Reference
	  Name			  "FIR\nInterpolation"
	  Ports			  [1, 1]
	  Position		  [535, 104, 600, 156]
	  SourceBlock		  "dspmlti3/FIR\nInterpolation"
	  SourceType		  "FIR Interpolation"
	  h			  "xFIR"
	  L			  "4"
	  framing		  "Maintain input frame size"
	  outputBufInitCond	  "0"
	}
	Block {
	  BlockType		  Reference
	  Name			  "FIR\nInterpolation1"
	  Ports			  [1, 1]
	  Position		  [535, 259, 600, 311]
	  SourceBlock		  "dspmlti3/FIR\nInterpolation"
	  SourceType		  "FIR Interpolation"
	  h			  "xFIR"
	  L			  "4"
	  framing		  "Maintain input frame size"
	  outputBufInitCond	  "0"
	}
	Block {
	  BlockType		  Product
	  Name			  "Product"
	  Ports			  [2, 1]
	  Position		  [800, 232, 840, 308]
	  InputSameDT		  off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product1"
	  Ports			  [2, 1]
	  Position		  [300, 51, 345, 84]
	  InputSameDT		  off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product2"
	  Ports			  [2, 1]
	  Position		  [300, 136, 345, 169]
	  InputSameDT		  off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product3"
	  Ports			  [2, 1]
	  Position		  [305, 216, 350, 249]
	  InputSameDT		  off
	}
	Block {
	  BlockType		  Product
	  Name			  "Product4"
	  Ports			  [2, 1]
	  Position		  [305, 291, 350, 324]
	  InputSameDT		  off
	}
	Block {
	  BlockType		  RealImagToComplex
	  Name			  "Real-Imag to\nComplex"
	  Ports			  [2, 1]
	  Position		  [700, 179, 745, 246]
	  Input			  "Real and imag"
	}
	Block {
	  BlockType		  Reference
	  Name			  "Subsystem"
	  Ports			  [0, 2]
	  Position		  [15, 14, 130, 121]
	  SourceBlock		  "pnsequence/Subsystem"
	  SourceType		  "Unknown"
	  xSeed			  "0"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum"
	  Ports			  [3, 1]
	  Position		  [140, 122, 170, 218]
	  ShowName		  off
	  Inputs		  "+++"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum1"
	  Ports			  [2, 1]
	  Position		  [140, 258, 170, 322]
	  ShowName		  off
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum2"
	  Ports			  [2, 1]
	  Position		  [440, 104, 470, 151]
	  ShowName		  off
	  Inputs		  "+-"
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	}
	Block {
	  BlockType		  Sum
	  Name			  "Sum3"
	  Ports			  [2, 1]
	  Position		  [435, 259, 465, 306]
	  ShowName		  off
	  InputSameDT		  off
	  OutDataTypeMode	  "Inherit via internal rule"
	}
	Block {
	  BlockType		  Outport
	  Name			  "Out1"
	  Position		  [895, 263, 925, 277]
	}
	Line {
	  SrcBlock		  "SCH2"
	  SrcPort		  1
	  DstBlock		  "Sum"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "PCH"
	  SrcPort		  1
	  DstBlock		  "Sum"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "DCCH"
	  SrcPort		  1
	  DstBlock		  "Sum"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "FCH"
	  SrcPort		  1
	  DstBlock		  "Sum1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "SCH1/CCCH/EACH"
	  SrcPort		  1
	  DstBlock		  "Sum1"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Subsystem"
	  SrcPort		  1
	  Points		  [100, 0; 0, 20]
	  Branch {
	    Points		    [0, 255]
	    DstBlock		    "Product4"
	    DstPort		    2
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	  Branch {
	    DstBlock		    "Product1"
	    DstPort		    1
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	Line {
	  SrcBlock		  "Subsystem"
	  SrcPort		  2
	  Points		  [125, 0; 0, 65]
	  Branch {
	    DstBlock		    "Product2"
	    DstPort		    2
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	  Branch {
	    Points		    [0, 65]
	    DstBlock		    "Product3"
	    DstPort		    1
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	Line {
	  SrcBlock		  "Sum"
	  SrcPort		  1
	  Points		  [45, 0; 0, -25; 50, 0]
	  Branch {
	    DstBlock		    "Product2"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -70]
	    DstBlock		    "Product1"
	    DstPort		    2
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	  SrcPort		  1
	  Points		  [0, 10; 80, 0]
	  Branch {
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	    DstBlock		    "Product3"
	    DstPort		    2
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	  Branch {
	    DstBlock		    "Product4"
	    DstPort		    1
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	  SrcBlock		  "Product1"
	  SrcPort		  1
	  Points		  [35, 0; 0, 45]
	  DstBlock		  "Sum2"
	  DstPort		  1
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	Line {
	  SrcBlock		  "Product3"
	  SrcPort		  1
	  Points		  [35, 0; 0, -95]
	  DstBlock		  "Sum2"
	  DstPort		  2
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	  SrcBlock		  "Product2"
	  SrcPort		  1
	  Points		  [70, 0]
	  DstBlock		  "Sum3"
	  DstPort		  1
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	  SrcBlock		  "Product4"
	  SrcPort		  1
	  Points		  [30, 0; 0, -15]
	  DstBlock		  "Sum3"
	  DstPort		  2
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	Line {
	  SrcBlock		  "Sum2"
	  SrcPort		  1
	  DstBlock		  "FIR\nInterpolation"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Sum3"
	  SrcPort		  1
	  DstBlock		  "FIR\nInterpolation1"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "FIR\nInterpolation"
	  SrcPort		  1
	  Points		  [40, 0; 0, 65]
	  DstBlock		  "Real-Imag to\nComplex"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "FIR\nInterpolation1"
	  SrcPort		  1
	  Points		  [40, 0; 0, -55]
	  DstBlock		  "Real-Imag to\nComplex"
	  DstPort		  2
	}
	Line {
	  SrcBlock		  "Real-Imag to\nComplex"
	  SrcPort		  1
	  Points		  [15, 0; 0, 35]
	  DstBlock		  "Product"
	  DstPort		  1
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	Line {
	  SrcBlock		  "In6"
	  SrcPort		  1
	  Points		  [20, 0; 0, -50]
	  DstBlock		  "Product"
	  DstPort		  2
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	  SrcBlock		  "Product"
	  SrcPort		  1
	  DstBlock		  "Out1"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Outport
      Name		      "Out1"
      Position		      [565, 243, 595, 257]
    }
    Line {
      SrcBlock		      "SCH2"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "PCH"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "DCCH"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Subsystem1"
      SrcPort		      1
      DstBlock		      "Out1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "FCH"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      4
    }
    Line {
      SrcBlock		      "SCH1/CCCH/EACH"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      5
    }
    Line {
      SrcBlock		      "In6"
      SrcPort		      1
      DstBlock		      "Subsystem1"
      DstPort		      6
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  }
}
💿 文件大小 59 K
👤 上传用户 luyibo54618
📂 所属分类通讯/手机编程
🏷️ 相关标签

#simulink #matlab #CDMA2 #仿真
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