ok.tan.qmsg

来自「quartus下实现的简易人羊白菜过河问题」· QMSG 代码 · 共 14 行 · 第 1/3 页

QMSG
14 行
字号
123
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 7 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "m " "Info: Assuming node m is an undefined clock" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } } { "c:/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "m" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register kongzhi:a1\|temp\[0\] register kongzhi:a1\|temp\[5\] 71.43 MHz 14.0 ns Internal " "Info: Clock clk has Internal fmax of 71.43 MHz between source register kongzhi:a1\|temp\[0\] and destination register kongzhi:a1\|temp\[5\] (period= 14.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.000 ns + Longest register register " "Info: + Longest register to register delay is 9.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns kongzhi:a1\|temp\[0\] 1 REG LC49 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC49; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[0\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { kongzhi:a1|temp[0] } "NODE_NAME" } } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns kongzhi:a1\|temp~397 2 COMB LC58 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC58; Fanout = 1; COMB Node = 'kongzhi:a1\|temp~397'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { kongzhi:a1|temp[0] kongzhi:a1|temp~397 } "NODE_NAME" } } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns kongzhi:a1\|temp\[5\] 3 REG LC59 18 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC59; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[5\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "1.000 ns" { kongzhi:a1|temp~397 kongzhi:a1|temp[5] } "NODE_NAME" } } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.000 ns 77.78 % " "Info: Total cell delay = 7.000 ns ( 77.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 22.22 % " "Info: Total interconnect delay = 2.000 ns ( 22.22 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "9.000 ns" { kongzhi:a1|temp[0] kongzhi:a1|temp~397 kongzhi:a1|temp[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns kongzhi:a1\|temp\[5\] 2 REG LC59 18 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC59; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[5\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "0.000 ns" { clk kongzhi:a1|temp[5] } "NODE_NAME" } } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[5] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 9 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 9; CLK Node = 'clk'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns kongzhi:a1\|temp\[0\] 2 REG LC49 18 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC49; Fanout = 18; REG Node = 'kongzhi:a1\|temp\[0\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "0.000 ns" { clk kongzhi:a1|temp[0] } "NODE_NAME" } } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[0] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[5] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "9.000 ns" { kongzhi:a1|temp[0] kongzhi:a1|temp~397 kongzhi:a1|temp[5] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[5] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "3.000 ns" { clk kongzhi:a1|temp[0] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "m register b1_temp\[2\] register count1\[2\] 40.0 MHz 25.0 ns Internal " "Info: Clock m has Internal fmax of 40.0 MHz between source register b1_temp\[2\] and destination register count1\[2\] (period= 25.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.000 ns + Longest register register " "Info: + Longest register to register delay is 20.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns b1_temp\[2\] 1 REG LC35 110 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC35; Fanout = 110; REG Node = 'b1_temp\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { b1_temp[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns process0~264 2 COMB LC101 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'process0~264'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { b1_temp[2] process0~264 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 9.000 ns process0~269 3 COMB LC102 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 9.000 ns; Loc. = LC102; Fanout = 1; COMB Node = 'process0~269'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "1.000 ns" { process0~264 process0~269 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 11.000 ns process0~261 4 COMB LC103 8 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 11.000 ns; Loc. = LC103; Fanout = 8; COMB Node = 'process0~261'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "2.000 ns" { process0~269 process0~261 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 19.000 ns count1\[2\]~956 5 COMB LC84 1 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 19.000 ns; Loc. = LC84; Fanout = 1; COMB Node = 'count1\[2\]~956'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { process0~261 count1[2]~956 } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 20.000 ns count1\[2\] 6 REG LC85 47 " "Info: 6: + IC(0.000 ns) + CELL(1.000 ns) = 20.000 ns; Loc. = LC85; Fanout = 47; REG Node = 'count1\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "1.000 ns" { count1[2]~956 count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.000 ns 80.00 % " "Info: Total cell delay = 16.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 20.00 % " "Info: Total interconnect delay = 4.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "20.000 ns" { b1_temp[2] process0~264 process0~269 process0~261 count1[2]~956 count1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m destination 10.000 ns + Shortest register " "Info: + Shortest clock path from clock m to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m 1 CLK PIN_4 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 14; CLK Node = 'm'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { m } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns count1\[2\] 2 REG LC85 47 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC85; Fanout = 47; REG Node = 'count1\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { m count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m count1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m source 10.000 ns - Longest register " "Info: - Longest clock path from clock m to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m 1 CLK PIN_4 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 14; CLK Node = 'm'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { m } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns b1_temp\[2\] 2 REG LC35 110 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC35; Fanout = 110; REG Node = 'b1_temp\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { m b1_temp[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m b1_temp[2] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m b1_temp[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "20.000 ns" { b1_temp[2] process0~264 process0~269 process0~261 count1[2]~956 count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m b1_temp[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TSU_RESULT" "count1\[2\] a\[3\] m 16.000 ns register " "Info: tsu for register count1\[2\] (data pin = a\[3\], clock pin = m) is 16.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "22.000 ns + Longest pin register " "Info: + Longest pin to register delay is 22.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns a\[3\] 1 PIN PIN_54 120 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_54; Fanout = 120; PIN Node = 'a\[3\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { a[3] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns process0~264 2 COMB LC101 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC101; Fanout = 1; COMB Node = 'process0~264'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { a[3] process0~264 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 11.000 ns process0~269 3 COMB LC102 1 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 11.000 ns; Loc. = LC102; Fanout = 1; COMB Node = 'process0~269'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "1.000 ns" { process0~264 process0~269 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 13.000 ns process0~261 4 COMB LC103 8 " "Info: 4: + IC(0.000 ns) + CELL(2.000 ns) = 13.000 ns; Loc. = LC103; Fanout = 8; COMB Node = 'process0~261'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "2.000 ns" { process0~269 process0~261 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 21.000 ns count1\[2\]~956 5 COMB LC84 1 " "Info: 5: + IC(2.000 ns) + CELL(6.000 ns) = 21.000 ns; Loc. = LC84; Fanout = 1; COMB Node = 'count1\[2\]~956'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { process0~261 count1[2]~956 } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 22.000 ns count1\[2\] 6 REG LC85 47 " "Info: 6: + IC(0.000 ns) + CELL(1.000 ns) = 22.000 ns; Loc. = LC85; Fanout = 47; REG Node = 'count1\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "1.000 ns" { count1[2]~956 count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns 81.82 % " "Info: Total cell delay = 18.000 ns ( 81.82 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 18.18 % " "Info: Total interconnect delay = 4.000 ns ( 18.18 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "22.000 ns" { a[3] process0~264 process0~269 process0~261 count1[2]~956 count1[2] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m destination 10.000 ns - Shortest register " "Info: - Shortest clock path from clock m to destination register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m 1 CLK PIN_4 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 14; CLK Node = 'm'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { m } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns count1\[2\] 2 REG LC85 47 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC85; Fanout = 47; REG Node = 'count1\[2\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { m count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m count1[2] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "22.000 ns" { a[3] process0~264 process0~269 process0~261 count1[2]~956 count1[2] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m count1[2] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "m b\[6\] lpm_counter:count2_rtl_0\|dffs\[0\] 34.000 ns register " "Info: tco from clock m to destination pin b\[6\] through register lpm_counter:count2_rtl_0\|dffs\[0\] is 34.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m source 10.000 ns + Longest register " "Info: + Longest clock path from clock m to source register is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns m 1 CLK PIN_4 14 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_4; Fanout = 14; CLK Node = 'm'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { m } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 10.000 ns lpm_counter:count2_rtl_0\|dffs\[0\] 2 REG LC75 50 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC75; Fanout = 50; REG Node = 'lpm_counter:count2_rtl_0\|dffs\[0\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { m lpm_counter:count2_rtl_0|dffs[0] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 80.00 % " "Info: Total cell delay = 8.000 ns ( 80.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 20.00 % " "Info: Total interconnect delay = 2.000 ns ( 20.00 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m lpm_counter:count2_rtl_0|dffs[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.000 ns + Longest register pin " "Info: + Longest register to pin delay is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count2_rtl_0\|dffs\[0\] 1 REG LC75 50 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC75; Fanout = 50; REG Node = 'lpm_counter:count2_rtl_0\|dffs\[0\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "" { lpm_counter:count2_rtl_0|dffs[0] } "NODE_NAME" } } } { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(6.000 ns) 8.000 ns display:a2\|b\[6\]~6727 2 COMB LC71 1 " "Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC71; Fanout = 1; COMB Node = 'display:a2\|b\[6\]~6727'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "8.000 ns" { lpm_counter:count2_rtl_0|dffs[0] display:a2|b[6]~6727 } "NODE_NAME" } } } { "D:/0510719/ok/display.vhd" "" "" { Text "D:/0510719/ok/display.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 10.000 ns display:a2\|b\[6\]~6668 3 COMB LC72 1 " "Info: 3: + IC(0.000 ns) + CELL(2.000 ns) = 10.000 ns; Loc. = LC72; Fanout = 1; COMB Node = 'display:a2\|b\[6\]~6668'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "2.000 ns" { display:a2|b[6]~6727 display:a2|b[6]~6668 } "NODE_NAME" } } } { "D:/0510719/ok/display.vhd" "" "" { Text "D:/0510719/ok/display.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(7.000 ns) 19.000 ns display:a2\|b\[6\]~6678 4 COMB LC8 1 " "Info: 4: + IC(2.000 ns) + CELL(7.000 ns) = 19.000 ns; Loc. = LC8; Fanout = 1; COMB Node = 'display:a2\|b\[6\]~6678'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "9.000 ns" { display:a2|b[6]~6668 display:a2|b[6]~6678 } "NODE_NAME" } } } { "D:/0510719/ok/display.vhd" "" "" { Text "D:/0510719/ok/display.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 23.000 ns b\[6\] 5 PIN PIN_9 0 " "Info: 5: + IC(0.000 ns) + CELL(4.000 ns) = 23.000 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'b\[6\]'" {  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "4.000 ns" { display:a2|b[6]~6678 b[6] } "NODE_NAME" } } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 82.61 % " "Info: Total cell delay = 19.000 ns ( 82.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 17.39 % " "Info: Total interconnect delay = 4.000 ns ( 17.39 % )" {  } {  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "23.000 ns" { lpm_counter:count2_rtl_0|dffs[0] display:a2|b[6]~6727 display:a2|b[6]~6668 display:a2|b[6]~6678 b[6] } "NODE_NAME" } } }  } 0}  } { { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "10.000 ns" { m lpm_counter:count2_rtl_0|dffs[0] } "NODE_NAME" } } } { "D:/0510719/ok/db/ok_cmp.qrpt" "" "" { Report "D:/0510719/ok/db/ok_cmp.qrpt" Compiler "ok" "UNKNOWN" "V1" "D:/0510719/ok/db/ok.quartus_db" { Floorplan "" "" "23.000 ns" { lpm_counter:count2_rtl_0|dffs[0] display:a2|b[6]~6727 display:a2|b[6]~6668 display:a2|b[6]~6678 b[6] } "NODE_NAME" } } }  } 0}
123

ok.tan.qmsg - 源码说明

本页面展示了「quartus下实现的简易人羊白菜过河问题」中的 ok.tan.qmsg 源码文件，采用 QMSG 编程语言编写，共 14 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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