ok.map.qmsg

quartus下实现的简易人羊白菜过河问题

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 31 14:26:27 2002 " "Info: Processing started: Thu Jan 31 14:26:27 2002" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off ok -c ok " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ok -c ok" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ok.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ok.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ok-vhdl " "Info: Found design unit 1: ok-vhdl" {  } { { "D:/0510719/ok/ok.vhd" "ok-vhdl" "" { Text "D:/0510719/ok/ok.vhd" 17 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ok " "Info: Found entity 1: ok" {  } { { "D:/0510719/ok/ok.vhd" "ok" "" { Text "D:/0510719/ok/ok.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "display.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file display.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 display-dd " "Info: Found design unit 1: display-dd" {  } { { "D:/0510719/ok/display.vhd" "display-dd" "" { Text "D:/0510719/ok/display.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 display " "Info: Found entity 1: display" {  } { { "D:/0510719/ok/display.vhd" "display" "" { Text "D:/0510719/ok/display.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "kongzhi.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file kongzhi.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 kongzhi-kk " "Info: Found design unit 1: kongzhi-kk" {  } { { "D:/0510719/ok/kongzhi.vhd" "kongzhi-kk" "" { Text "D:/0510719/ok/kongzhi.vhd" 12 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 kongzhi " "Info: Found entity 1: kongzhi" {  } { { "D:/0510719/ok/kongzhi.vhd" "kongzhi" "" { Text "D:/0510719/ok/kongzhi.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "count2\[0\]~12 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: count2\[0\]~12" {  } { { "D:/0510719/ok/ok.vhd" "" "count2\[0\]~12" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } } { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } } { "D:/0510719/复件 ok/kongzhi.vhd" "" "" { Text "D:/0510719/复件 ok/kongzhi.vhd" 20 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "b2_temp\[3\] b1_temp\[3\] " "Info: Duplicate register b2_temp\[3\] merged to single register b1_temp\[3\], power-up level changed" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "b2_temp\[2\] b1_temp\[2\] " "Info: Duplicate register b2_temp\[2\] merged to single register b1_temp\[2\], power-up level changed" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "b2_temp\[1\] b1_temp\[1\] " "Info: Duplicate register b2_temp\[1\] merged to single register b1_temp\[1\], power-up level changed" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0} { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "b2_temp\[0\] b1_temp\[0\] " "Info: Duplicate register b2_temp\[0\] merged to single register b1_temp\[0\], power-up level changed" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 63 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0}  } {  } 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "4 " "Warning: Design contains 4 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "level\[3\] " "Warning: No output dependent on input pin level\[3\]" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 14 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "level\[2\] " "Warning: No output dependent on input pin level\[2\]" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 14 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "level\[1\] " "Warning: No output dependent on input pin level\[1\]" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 14 -1 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "level\[0\] " "Warning: No output dependent on input pin level\[0\]" {  } { { "D:/0510719/ok/ok.vhd" "" "" { Text "D:/0510719/ok/ok.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "151 " "Info: Implemented 151 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "21 " "Info: Implemented 21 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "93 " "Info: Implemented 93 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "26 " "Info: Implemented 26 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 31 14:26:40 2002 " "Info: Processing ended: Thu Jan 31 14:26:40 2002" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0}  } {  } 0}