qam.map.rpt

实现QAM调制功能和QAM解调功能的代码.

;     -- 3 input functions                    ; 63                                 ;
;     -- <=2 input functions                  ; 16                                 ;
;         -- Combinational cells for routing  ; 0                                  ;
; Logic elements by mode                      ;                                    ;
;     -- normal mode                          ; 57                                 ;
;     -- arithmetic mode                      ; 49                                 ;
; Total registers                             ; 33                                 ;
; I/O pins                                    ; 11                                 ;
; Maximum fan-out node                        ; compose:inst5|cnt_4:inst1|count[2] ;
; Maximum fan-out                             ; 39                                 ;
; Total fan-out                               ; 393                                ;
; Average fan-out                             ; 2.62                               ;
+---------------------------------------------+------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                             ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name             ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------+
; |QAM                       ; 106 (0)           ; 33 (0)       ; 0           ; 0    ; 0            ; 0       ; 0         ; 11   ; 0            ; |QAM                            ;
;    |74393:inst10|          ; 5 (5)             ; 5 (5)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|74393:inst10               ;
;    |DIV_CLK_2:inst15|      ; 1 (1)             ; 1 (1)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|DIV_CLK_2:inst15           ;
;    |M_GENERAToR:inst|      ; 1 (1)             ; 23 (23)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|M_GENERAToR:inst           ;
;    |compose:inst5|         ; 99 (0)            ; 4 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5              ;
;       |4xuan1:inst3|       ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|4xuan1:inst3 ;
;       |add:inst43|         ; 56 (56)           ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|add:inst43   ;
;       |cnt_4:inst1|        ; 4 (4)             ; 4 (4)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|cnt_4:inst1  ;
;       |cos1:inst4|         ; 4 (4)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|cos1:inst4   ;
;       |cos2:inst29|        ; 3 (3)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|cos2:inst29  ;
;       |cos3:inst30|        ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|cos3:inst30  ;
;       |sin1:inst32|        ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|sin1:inst32  ;
;       |sin2:inst33|        ; 6 (6)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|sin2:inst33  ;
;       |sin3:inst34|        ; 5 (5)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|sin3:inst34  ;
;       |sin:inst31|         ; 5 (5)             ; 0 (0)        ; 0           ; 0    ; 0            ; 0       ; 0         ; 0    ; 0            ; |QAM|compose:inst5|sin:inst31   ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 33    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 15 09:18:06 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off QAM -c QAM
Info: Found 1 design units, including 1 entities, in source file M_GENERAToR.tdf
    Info: Found entity 1: M_GENERAToR
Info: Found 1 design units, including 1 entities, in source file QAM.bdf
    Info: Found entity 1: QAM
Info: Found 1 design units, including 1 entities, in source file table1.tdf
    Info: Found entity 1: table1
Info: Found 1 design units, including 1 entities, in source file cnt_4.tdf
    Info: Found entity 1: cnt_4
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file cos.tdf
    Info: Found entity 1: cos
Info: Found 1 design units, including 1 entities, in source file add.tdf
    Info: Found entity 1: add
Info: Found 1 design units, including 1 entities, in source file DIV_CLK_2.tdf
    Info: Found entity 1: DIV_CLK_2
Info: Found 1 design units, including 1 entities, in source file zhuanhuan.tdf
    Info: Found entity 1: zhuanhuan
Info: Found 1 design units, including 1 entities, in source file zhuanhuan1.tdf
    Info: Found entity 1: zhuanhuan1
Info: Found 1 design units, including 1 entities, in source file zhuanhuan2.tdf
    Info: Found entity 1: zhuanhuan2
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file cos1.tdf
    Info: Found entity 1: cos1
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file cos2.tdf
    Info: Found entity 1: cos2
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file cos3.tdf
    Info: Found entity 1: cos3
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file sin.tdf
    Info: Found entity 1: sin
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file sin1.tdf
    Info: Found entity 1: sin1
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file sin2.tdf
    Info: Found entity 1: sin2
Warning: Symbolic name "Q" is used but not defined as a group -- attempted to use existing nodes
Info: Found 1 design units, including 1 entities, in source file sin3.tdf
    Info: Found entity 1: sin3
Info: Found 1 design units, including 1 entities, in source file 4xuan1.tdf
    Info: Found entity 1: 4xuan1
Info: Elaborating entity "QAM" for the top level hierarchy
Info: Elaborating entity "M_GENERAToR" for hierarchy "M_GENERAToR:inst"
Info: Found 1 design units, including 1 entities, in source file ../../quartus60/libraries/others/maxplus2/74393.bdf
    Info: Found entity 1: 74393
Info: Elaborating entity "74393" for hierarchy "74393:inst10"
Info: Elaborated megafunction instantiation "74393:inst10"
Warning: Using design file compose.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: compose
Info: Elaborating entity "compose" for hierarchy "compose:inst5"
Info: Elaborating entity "add" for hierarchy "compose:inst5|add:inst43"
Info: Elaborating entity "zhuanhuan2" for hierarchy "compose:inst5|zhuanhuan2:inst35"
Info: Elaborating entity "cos" for hierarchy "compose:inst5|cos:inst27"
Info: Elaborating entity "zhuanhuan1" for hierarchy "compose:inst5|zhuanhuan1:inst15"
Info: Elaborating entity "4xuan1" for hierarchy "compose:inst5|4xuan1:inst"
Info: Elaborating entity "cnt_4" for hierarchy "compose:inst5|cnt_4:inst2"
Info: Elaborating entity "zhuanhuan" for hierarchy "compose:inst5|zhuanhuan:inst5"
Info: Elaborating entity "table1" for hierarchy "compose:inst5|table1:inst9"
Info: Elaborating entity "cos1" for hierarchy "compose:inst5|cos1:inst4"
Info: Elaborating entity "cos2" for hierarchy "compose:inst5|cos2:inst29"
Info: Elaborating entity "cos3" for hierarchy "compose:inst5|cos3:inst30"
Info: Elaborating entity "sin" for hierarchy "compose:inst5|sin:inst31"
Info: Elaborating entity "sin1" for hierarchy "compose:inst5|sin1:inst32"
Info: Elaborating entity "sin2" for hierarchy "compose:inst5|sin2:inst33"
Info: Elaborating entity "sin3" for hierarchy "compose:inst5|sin3:inst34"
Info: Elaborating entity "DIV_CLK_2" for hierarchy "DIV_CLK_2:inst15"
Warning: Using design file d.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: d
Info: Elaborating entity "d" for hierarchy "d:inst3"
Warning: Using design file fenli.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: fenli
Info: Elaborating entity "fenli" for hierarchy "fenli:inst2"
Warning: Using design file lock.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: lock
Info: Elaborating entity "lock" for hierarchy "lock:inst11"
Info: Duplicate registers merged to single register
    Info: Duplicate register "compose:inst5|cnt_4:inst2|count[3]" merged to single register "compose:inst5|cnt_4:inst1|count[3]"
    Info: Duplicate register "compose:inst5|cnt_4:inst2|count[2]" merged to single register "compose:inst5|cnt_4:inst1|count[2]"
    Info: Duplicate register "compose:inst5|cnt_4:inst2|count[1]" merged to single register "compose:inst5|cnt_4:inst1|count[1]"
    Info: Duplicate register "compose:inst5|cnt_4:inst2|count[0]" merged to single register "compose:inst5|cnt_4:inst1|count[0]"
Info: Implemented 139 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 10 output pins
    Info: Implemented 128 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Processing ended: Sun Jun 15 09:18:15 2008
    Info: Elapsed time: 00:00:10