qam.tan.rpt

实现QAM调制功能和QAM解调功能的代码.

; N/A   ; None         ; 15.667 ns  ; compose:inst5|cnt_4:inst1|count[3] ; Q[2]  ; CNT_CLK    ;
; N/A   ; None         ; 15.652 ns  ; compose:inst5|cnt_4:inst1|count[3] ; Q[1]  ; CNT_CLK    ;
; N/A   ; None         ; 15.649 ns  ; compose:inst5|cnt_4:inst1|count[2] ; Q[2]  ; CNT_CLK    ;
; N/A   ; None         ; 15.634 ns  ; compose:inst5|cnt_4:inst1|count[2] ; Q[1]  ; CNT_CLK    ;
; N/A   ; None         ; 9.479 ns   ; M_GENERAToR:inst|bit[22]           ; mout  ; CNT_CLK    ;
; N/A   ; None         ; 7.555 ns   ; 74393:inst10|28                    ; mout1 ; CNT_CLK    ;
+-------+--------------+------------+------------------------------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Sun Jun 15 09:18:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off QAM -c QAM --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CNT_CLK" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "DIV_CLK_2:inst15|clk_out" as buffer
    Info: Detected ripple clock "74393:inst10|9" as buffer
    Info: Detected ripple clock "74393:inst10|28" as buffer
Info: Clock "CNT_CLK" Internal fmax is restricted to 420.17 MHz between source register "M_GENERAToR:inst|bit[2]" and destination register "M_GENERAToR:inst|bit[3]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.961 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 1; REG Node = 'M_GENERAToR:inst|bit[2]'
            Info: 2: + IC(0.728 ns) + CELL(0.149 ns) = 0.877 ns; Loc. = LCCOMB_X10_Y12_N12; Fanout = 1; COMB Node = 'M_GENERAToR:inst|bit[3]~feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.961 ns; Loc. = LCFF_X10_Y12_N13; Fanout = 1; REG Node = 'M_GENERAToR:inst|bit[3]'
            Info: Total cell delay = 0.233 ns ( 24.25 % )
            Info: Total interconnect delay = 0.728 ns ( 75.75 % )
        Info: - Smallest clock skew is -0.003 ns
            Info: + Shortest clock path from clock "CNT_CLK" to destination register is 5.535 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CNT_CLK'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CNT_CLK~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N3; Fanout = 2; REG Node = '74393:inst10|9'
                Info: 4: + IC(0.293 ns) + CELL(0.787 ns) = 3.680 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 3; REG Node = '74393:inst10|28'
                Info: 5: + IC(0.589 ns) + CELL(0.000 ns) = 4.269 ns; Loc. = CLKCTRL_G5; Fanout = 23; COMB Node = '74393:inst10|28~clkctrl'
                Info: 6: + IC(0.729 ns) + CELL(0.537 ns) = 5.535 ns; Loc. = LCFF_X10_Y12_N13; Fanout = 1; REG Node = 'M_GENERAToR:inst|bit[3]'
                Info: Total cell delay = 3.100 ns ( 56.01 % )
                Info: Total interconnect delay = 2.435 ns ( 43.99 % )
            Info: - Longest clock path from clock "CNT_CLK" to source register is 5.538 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CNT_CLK'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CNT_CLK~clkctrl'
                Info: 3: + IC(0.702 ns) + CELL(0.787 ns) = 2.600 ns; Loc. = LCFF_X27_Y7_N3; Fanout = 2; REG Node = '74393:inst10|9'
                Info: 4: + IC(0.293 ns) + CELL(0.787 ns) = 3.680 ns; Loc. = LCFF_X27_Y7_N7; Fanout = 3; REG Node = '74393:inst10|28'
                Info: 5: + IC(0.589 ns) + CELL(0.000 ns) = 4.269 ns; Loc. = CLKCTRL_G5; Fanout = 23; COMB Node = '74393:inst10|28~clkctrl'
                Info: 6: + IC(0.732 ns) + CELL(0.537 ns) = 5.538 ns; Loc. = LCFF_X12_Y12_N9; Fanout = 1; REG Node = 'M_GENERAToR:inst|bit[2]'
                Info: Total cell delay = 3.100 ns ( 55.98 % )
                Info: Total interconnect delay = 2.438 ns ( 44.02 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "CNT_CLK" to destination pin "Q[6]" through register "compose:inst5|cnt_4:inst1|count[1]" is 18.187 ns
    Info: + Longest clock path from clock "CNT_CLK" to source register is 5.021 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'CNT_CLK'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 5; COMB Node = 'CNT_CLK~clkctrl'
        Info: 3: + IC(0.715 ns) + CELL(0.787 ns) = 2.613 ns; Loc. = LCFF_X1_Y11_N13; Fanout = 2; REG Node = 'DIV_CLK_2:inst15|clk_out'
        Info: 4: + IC(1.171 ns) + CELL(0.000 ns) = 3.784 ns; Loc. = CLKCTRL_G0; Fanout = 4; COMB Node = 'DIV_CLK_2:inst15|clk_out~clkctrl'
        Info: 5: + IC(0.700 ns) + CELL(0.537 ns) = 5.021 ns; Loc. = LCFF_X24_Y6_N11; Fanout = 30; REG Node = 'compose:inst5|cnt_4:inst1|count[1]'
        Info: Total cell delay = 2.313 ns ( 46.07 % )
        Info: Total interconnect delay = 2.708 ns ( 53.93 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 12.916 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y6_N11; Fanout = 30; REG Node = 'compose:inst5|cnt_4:inst1|count[1]'
        Info: 2: + IC(0.427 ns) + CELL(0.398 ns) = 0.825 ns; Loc. = LCCOMB_X24_Y6_N18; Fanout = 2; COMB Node = 'compose:inst5|4xuan1:inst3|_~391'
        Info: 3: + IC(0.981 ns) + CELL(0.420 ns) = 2.226 ns; Loc. = LCCOMB_X26_Y7_N24; Fanout = 8; COMB Node = 'compose:inst5|sin:inst31|_~6'
        Info: 4: + IC(0.479 ns) + CELL(0.393 ns) = 3.098 ns; Loc. = LCCOMB_X25_Y7_N0; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_1~97'
        Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 3.508 ns; Loc. = LCCOMB_X25_Y7_N2; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_1~98'
        Info: 6: + IC(0.460 ns) + CELL(0.414 ns) = 4.382 ns; Loc. = LCCOMB_X25_Y7_N18; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_3~99'
        Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 4.453 ns; Loc. = LCCOMB_X25_Y7_N20; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_3~101'
        Info: 8: + IC(0.000 ns) + CELL(0.410 ns) = 4.863 ns; Loc. = LCCOMB_X25_Y7_N22; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_3~102'
        Info: 9: + IC(0.733 ns) + CELL(0.414 ns) = 6.010 ns; Loc. = LCCOMB_X25_Y8_N6; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_5~103'
        Info: 10: + IC(0.000 ns) + CELL(0.410 ns) = 6.420 ns; Loc. = LCCOMB_X25_Y8_N8; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|op_5~104'
        Info: 11: + IC(0.699 ns) + CELL(0.414 ns) = 7.533 ns; Loc. = LCCOMB_X24_Y8_N24; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|Q[4]~25'
        Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 7.604 ns; Loc. = LCCOMB_X24_Y8_N26; Fanout = 2; COMB Node = 'compose:inst5|add:inst43|Q[5]~27'
        Info: 13: + IC(0.000 ns) + CELL(0.410 ns) = 8.014 ns; Loc. = LCCOMB_X24_Y8_N28; Fanout = 1; COMB Node = 'compose:inst5|add:inst43|Q[6]~28'
        Info: 14: + IC(2.250 ns) + CELL(2.652 ns) = 12.916 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'Q[6]'
        Info: Total cell delay = 6.887 ns ( 53.32 % )
        Info: Total interconnect delay = 6.029 ns ( 46.68 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Sun Jun 15 09:18:47 2008
    Info: Elapsed time: 00:00:01