lpc213x.h

ucos移植到arm的源代码

/**************************************************************************
*                                                                         *
*   PROJECT     : ARM port for uC/OS-II                                   *
*                                                                         *
*   MODULE      : LPC213X.h                                               *
*                                                                         *
*   AUTHOR      : Michael Anburaj                                         *
*                 URL  : http://geocities.com/michaelanburaj/             *
*                 EMAIL: [e-mail]                       *
*                                                                         *
*   SPONSORS    : Thanks to Martin Li ([e-mail]) & Don Williams    *
*                 ([e-mail]) for sponsoring hardware.            *
*                                                                         *
*   PROCESSOR   : LPC213x (32 bit ARM7TDMI-S RISC core from Philips)      *
*                                                                         *
*   TOOL-CHAIN  : SDT 2.51, ADS 1.2 or GCC                                *
*                                                                         *
*   DESCRIPTION :                                                         *
*   LPC213x processor register definition header file.                    *
*                                                                         *
**************************************************************************/


#ifndef __LPC213X_H__
#define __LPC213X_H__


#include "frmwrk.h"


#ifdef __cplusplus
extern "C" {
#endif


/* ********************************************************************* */
/* Module configuration */


/* ********************************************************************* */
/* Interface macro & data definition */

// Memory Accelerator Module (MAM)
#define rMAMCR     (*(volatile unsigned char *)(SFR_BADDR + 0x1fc000))   //MAM Control Register
#define rMAMTIM    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc004))   //MAM Timing control
#define rMEMMAP    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc040))   //Memory mapping control

// Phase Locked Loop (PLL)
#define rPLLCON    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc080))   //PLL control
#define rPLLCFG    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc084))   //PLL configuration
#define rPLLSTAT   (*(volatile unsigned short *)(SFR_BADDR + 0x1fc088))  //PLL status
#define rPLLFEED   (*(volatile unsigned char *)(SFR_BADDR + 0x1fc08c))   //PLL feed

// rPLLCON Register
#define BIT_PLLCON_PLLE  (0x1<<0)                                 //PLL Enable
#define BIT_PLLCON_PLLC  (0x1<<1)                                 //PLL Connect

// rPLLSTAT Register
#define BIT_PLLSTAT_LOCK (1 << 10)                                //PLL Lock Status Bit

// Power Control
#define rPCON      (*(volatile unsigned char *)(SFR_BADDR + 0x1fc0c0))   //Power control
#define rPCONP     (*(volatile unsigned *)(SFR_BADDR + 0x1fc0c4))        //Power control for peripherals

// VPB Divider
#define rVPBDIV    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc100))   //VPB divider control

// External Interrupts
#define rEXTINT    (*(volatile unsigned char *)(SFR_BADDR + 0x1fc140))   //External interrupt flag
#define rINTWAKE   (*(volatile unsigned char *)(SFR_BADDR + 0x1fc144))   //External interrupt wakeup
#define rEXTMODE   (*(volatile unsigned char *)(SFR_BADDR + 0x1fc148))   //External interrupt mode
#define rEXTPOLAR  (*(volatile unsigned char *)(SFR_BADDR + 0x1fc14c))   //External interrupt polarity

// Reset
#define rRSID      (*(volatile unsigned char *)(SFR_BADDR + 0x1fc180))   //Reset source identification

// Code Security / Debugging
#define rCSPR      (*(volatile unsigned char *)(SFR_BADDR + 0x1fc184))   //Code security protection


// VIC
#define VIC_BADDR 0xfffff000
#define rVICIRQStatus  (*(volatile unsigned *)(VIC_BADDR + 0x000))       //IRQ Status
#define rVICFIQStatus  (*(volatile unsigned *)(VIC_BADDR + 0x004))       //FIQ Status
#define rVICRawIntr    (*(volatile unsigned *)(VIC_BADDR + 0x008))       //Raw Interrupt Status
#define rVICIntSelect  (*(volatile unsigned *)(VIC_BADDR + 0x00c))       //Interrupt Select
#define rVICIntEnable  (*(volatile unsigned *)(VIC_BADDR + 0x010))       //Interrupt Enable
#define rVICIntEnClr   (*(volatile unsigned *)(VIC_BADDR + 0x014))       //Interrupt Enable Clear
#define rVICSoftInt    (*(volatile unsigned *)(VIC_BADDR + 0x018))       //Software Interrupt
#define rVICSoftIntClear (*(volatile unsigned *)(VIC_BADDR + 0x01c))     //Software Interrupt Clear
#define rVICProtection (*(volatile unsigned *)(VIC_BADDR + 0x020))       //Protection enable
#define rVICVectAddr   (*(volatile unsigned *)(VIC_BADDR + 0x030))       //Vector Address
#define rVICDefVectAddr (*(volatile unsigned *)(VIC_BADDR + 0x034))      //Default Vector Address
#define rVICVectAddr0  (*(volatile unsigned *)(VIC_BADDR + 0x100))       //Vector address 0 register
#define rVICVectAddr1  (*(volatile unsigned *)(VIC_BADDR + 0x104))       //Vector address 1 register
#define rVICVectAddr2  (*(volatile unsigned *)(VIC_BADDR + 0x108))       //Vector address 2 register
#define rVICVectAddr3  (*(volatile unsigned *)(VIC_BADDR + 0x10c))       //Vector address 3 register
#define rVICVectAddr4  (*(volatile unsigned *)(VIC_BADDR + 0x110))       //Vector address 4 register
#define rVICVectAddr5  (*(volatile unsigned *)(VIC_BADDR + 0x114))       //Vector address 5 register
#define rVICVectAddr6  (*(volatile unsigned *)(VIC_BADDR + 0x118))       //Vector address 6 register
#define rVICVectAddr7  (*(volatile unsigned *)(VIC_BADDR + 0x11c))       //Vector address 7 register
#define rVICVectAddr8  (*(volatile unsigned *)(VIC_BADDR + 0x120))       //Vector address 8 register
#define rVICVectAddr9  (*(volatile unsigned *)(VIC_BADDR + 0x124))       //Vector address 9 register
#define rVICVectAddr10 (*(volatile unsigned *)(VIC_BADDR + 0x128))       //Vector address 10 register
#define rVICVectAddr11 (*(volatile unsigned *)(VIC_BADDR + 0x12c))       //Vector address 11 register
#define rVICVectAddr12 (*(volatile unsigned *)(VIC_BADDR + 0x130))       //Vector address 12 register
#define rVICVectAddr13 (*(volatile unsigned *)(VIC_BADDR + 0x134))       //Vector address 13 register
#define rVICVectAddr14 (*(volatile unsigned *)(VIC_BADDR + 0x138))       //Vector address 14 register
#define rVICVectAddr15 (*(volatile unsigned *)(VIC_BADDR + 0x13c))       //Vector address 15 register
#define rVICVectCntl0  (*(volatile unsigned *)(VIC_BADDR + 0x200))       //Vector control 0 register
#define rVICVectCntl1  (*(volatile unsigned *)(VIC_BADDR + 0x204))       //Vector control 1 register
#define rVICVectCntl2  (*(volatile unsigned *)(VIC_BADDR + 0x208))       //Vector control 2 register
#define rVICVectCntl3  (*(volatile unsigned *)(VIC_BADDR + 0x20c))       //Vector control 3 register
#define rVICVectCntl4  (*(volatile unsigned *)(VIC_BADDR + 0x210))       //Vector control 4 register
#define rVICVectCntl5  (*(volatile unsigned *)(VIC_BADDR + 0x214))       //Vector control 5 register
#define rVICVectCntl6  (*(volatile unsigned *)(VIC_BADDR + 0x218))       //Vector control 6 register
#define rVICVectCntl7  (*(volatile unsigned *)(VIC_BADDR + 0x21c))       //Vector control 7 register
#define rVICVectCntl8  (*(volatile unsigned *)(VIC_BADDR + 0x220))       //Vector control 8 register
#define rVICVectCntl9  (*(volatile unsigned *)(VIC_BADDR + 0x224))       //Vector control 9 register
#define rVICVectCntl10 (*(volatile unsigned *)(VIC_BADDR + 0x228))       //Vector control 10 register
#define rVICVectCntl11 (*(volatile unsigned *)(VIC_BADDR + 0x22c))       //Vector control 11 register
#define rVICVectCntl12 (*(volatile unsigned *)(VIC_BADDR + 0x230))       //Vector control 12 register
#define rVICVectCntl13 (*(volatile unsigned *)(VIC_BADDR + 0x234))       //Vector control 13 register
#define rVICVectCntl14 (*(volatile unsigned *)(VIC_BADDR + 0x238))       //Vector control 14 register
#define rVICVectCntl15 (*(volatile unsigned *)(VIC_BADDR + 0x23c))       //Vector control 15 register


// GPIO 
#define rIOPIN0    (*(volatile unsigned *)(SFR_BADDR + 0x28000))         //GPIO pin value
#define rIOSET0    (*(volatile unsigned *)(SFR_BADDR + 0x28004))         //Output value SET
#define rIODIR0    (*(volatile unsigned *)(SFR_BADDR + 0x28008))         //Direction control
#define rIOCLR0    (*(volatile unsigned *)(SFR_BADDR + 0x2800c))         //Output value CLEAR
#define rIOPIN1    (*(volatile unsigned *)(SFR_BADDR + 0x28010))         //GPIO pin value
#define rIOSET1    (*(volatile unsigned *)(SFR_BADDR + 0x28014))         //Output value SET
#define rIODIR1    (*(volatile unsigned *)(SFR_BADDR + 0x28018))         //Direction control
#define rIOCLR1    (*(volatile unsigned *)(SFR_BADDR + 0x2801c))         //Output value CLEAR

#define rPINSEL0   (*(volatile unsigned *)(SFR_BADDR + 0x2c000))         //Pin function select 0
#define rPINSEL1   (*(volatile unsigned *)(SFR_BADDR + 0x2c004))         //Pin function select 1
#define rPINSEL2   (*(volatile unsigned *)(SFR_BADDR + 0x2c014))         //Pin function select 2

// PINSEL0 values
#define VAL_PINSEL0_U0      (0x5<<0)                                     // PINSEL0 Value for UART0
#define MSK_PINSEL0_U0      (0xf<<0)                                     // PINSEL0 Mask for UART0
#define VAL_PINSEL0_U1      (0x5<<16)                                    // PINSEL0 Value for UART1
#define MSK_PINSEL0_U1      (0xf<<16)                                    // PINSEL0 Mask for UART1


//UART0
#define rU0RBR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c000))    //RO - Receiver Buffer
#define rU0THR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c000))    //WO - Transmit Holding
#define rU0IER     (*(volatile unsigned char *)(SFR_BADDR + 0x0c004))    //RW - Interrupt Enable
#define rU0IIR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c008))    //RO - Interrupt ID
#define rU0FCR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c008))    //WO - FIFO Control
#define rU0LCR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c00c))    //RW - Line Control
#define rU0LSR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c014))    //RO - Line Status
#define rU0SCR     (*(volatile unsigned char *)(SFR_BADDR + 0x0c01c))    //RW - Scratch Pad
// DLAB = 1
#define rU0DLL     (*(volatile unsigned char *)(SFR_BADDR + 0x0c000))    //RW - Divisor Latch LSB
#define rU0DLM     (*(volatile unsigned char *)(SFR_BADDR + 0x0c004))    //RW - Divisor Latch MSB
#define rU0TER     (*(volatile unsigned char *)(SFR_BADDR + 0x0c030))    //RW - Transmit enable

//UART1
#define rU1RBR     (*(volatile unsigned char *)(SFR_BADDR + 0x10000))    //RO - Receiver Buffer
#define rU1THR     (*(volatile unsigned char *)(SFR_BADDR + 0x10000))    //WO - Transmit Holding
#define rU1IER     (*(volatile unsigned char *)(SFR_BADDR + 0x10004))    //RW - Interrupt Enable
#define rU1IIR     (*(volatile unsigned char *)(SFR_BADDR + 0x10008))    //RO - Interrupt ID
#define rU1FCR     (*(volatile unsigned char *)(SFR_BADDR + 0x10008))    //WO - FIFO Control
#define rU1LCR     (*(volatile unsigned char *)(SFR_BADDR + 0x1000c))    //RW - Line Control
#define rU1MCR     (*(volatile unsigned char *)(SFR_BADDR + 0x10010))    //RW - Modem Control
#define rU1LSR     (*(volatile unsigned char *)(SFR_BADDR + 0x10014))    //RO - Line Status
#define rU1MSR     (*(volatile unsigned char *)(SFR_BADDR + 0x10018))    //RO - Modem Status
#define rU1SCR     (*(volatile unsigned char *)(SFR_BADDR + 0x1001c))    //RW - Scratch Pad
// DLAB = 1
#define rU1DLL     (*(volatile unsigned char *)(SFR_BADDR + 0x10000))    //RW - Divisor Latch LSB
#define rU1DLM     (*(volatile unsigned char *)(SFR_BADDR + 0x10004))    //RW - Divisor Latch MSB
#define rU1TER     (*(volatile unsigned char *)(SFR_BADDR + 0x10030))    //RW - Transmit enable


// I2C0
#define rI2C0CONSET (*(volatile unsigned char *)(SFR_BADDR + 0x1c000))   //I2C 0 Control Set
#define rI2C0STAT  (*(volatile unsigned char *)(SFR_BADDR + 0x1C004))    //I2C 0 Status
#define rI2C0DAT   (*(volatile unsigned char *)(SFR_BADDR + 0x1c008))    //I2C 0 Data
#define rI2C0ADR   (*(volatile unsigned char *)(SFR_BADDR + 0x1C00c))    //I2C 0 Slave Address
#define rI2C0SCLH  (*(volatile unsigned short *)(SFR_BADDR + 0x1c010))   //SCL 0 Duty Cycle Register High Half Word
#define rI2C0SCLL  (*(volatile unsigned short *)(SFR_BADDR + 0x1c014))   //SCL 0 Duty Cycle Register Low Half Word
#define rI2C0CONCLR (*(volatile unsigned char *)(SFR_BADDR + 0x1c018))   //I2C 0 Control Clear

// I2C1
#define rI2C1CONSET (*(volatile unsigned char *)(SFR_BADDR + 0x5c000))   //I2C 1 Control Set
#define rI2C1STAT  (*(volatile unsigned char *)(SFR_BADDR + 0x5c004))    //I2C 1 Status
#define rI2C1DAT   (*(volatile unsigned char *)(SFR_BADDR + 0x5C008))    //I2C 1 Data
#define rI2C1ADR   (*(volatile unsigned char *)(SFR_BADDR + 0x5c00c))    //I2C 1 Slave Address
#define rI2C1SCLH  (*(volatile unsigned short *)(SFR_BADDR + 0x5c010))   //SCL 1 Duty Cycle Register High Half Word
#define rI2C1SCLL  (*(volatile unsigned short *)(SFR_BADDR + 0x5C014))   //SCL 1 Duty Cycle Register Low Half Word
#define rI2C1CONCLR (*(volatile unsigned char *)(SFR_BADDR + 0x5C018))   //I2C 1 Control Clear


// SPI0
#define rS0SPCR    (*(volatile unsigned char *)(SFR_BADDR + 0x20000))    //SPI 0 Control
#define rS0SPSR    (*(volatile unsigned char *)(SFR_BADDR + 0x20004))    //SPI 0 Status
#define rS0SPDR    (*(volatile unsigned char *)(SFR_BADDR + 0x20008))    //SPI 0 Data
#define rS0SPCCR   (*(volatile unsigned char *)(SFR_BADDR + 0x2000c))    //SPI 0 Clock Counter
#define rS0SPINT   (*(volatile unsigned char *)(SFR_BADDR + 0x2001c))    //SPI 0 Interrupt Flag

// SPI1 (SSP)
#define rSSPCR0    (*(volatile unsigned char *)(SFR_BADDR + 0x68000))    //SSP Control 0
#define rSSPCR1    (*(volatile unsigned char *)(SFR_BADDR + 0x68004))    //SSP Control 1
#define rSSPDR     (*(volatile unsigned char *)(SFR_BADDR + 0x68008))    //SSP Data
#define rSSPSR     (*(volatile unsigned char *)(SFR_BADDR + 0x6800c))    //SSP Status
#define rSSPCPSR   (*(volatile unsigned char *)(SFR_BADDR + 0x68010))    //SSP Clock Prescale
#define rSSPIMSC   (*(volatile unsigned char *)(SFR_BADDR + 0x68014))    //SSP Interrupt Mask Set & Clear
#define rSSPRIS    (*(volatile unsigned char *)(SFR_BADDR + 0x68018))    //SSP Raw Interrupt Status
#define rSSPMIS    (*(volatile unsigned char *)(SFR_BADDR + 0x6801c))    //SSP Masked Interrupt Status
#define rSSPICR    (*(volatile unsigned char *)(SFR_BADDR + 0x68020))    //SSP Interrupt Clear


// Timer 0
#define rT0IR      (*(volatile unsigned *)(SFR_BADDR + 0x04000))         //Interrupt Register
#define rT0TCR     (*(volatile unsigned *)(SFR_BADDR + 0x04004))         //Timer Control
#define rT0TC      (*(volatile unsigned *)(SFR_BADDR + 0x04008))         //Timer Counter
#define rT0PR      (*(volatile unsigned *)(SFR_BADDR + 0x0400c))         //Prescale Register
#define rT0PC      (*(volatile unsigned *)(SFR_BADDR + 0x04010))         //Prescale Counter
#define rT0MCR     (*(volatile unsigned *)(SFR_BADDR + 0x04014))         //Match Control
#define rT0MR0     (*(volatile unsigned *)(SFR_BADDR + 0x04018))         //Match Register 0
#define rT0MR1     (*(volatile unsigned *)(SFR_BADDR + 0x0401c))         //Match Register 1
#define rT0MR2     (*(volatile unsigned *)(SFR_BADDR + 0x04020))         //Match Register 2
#define rT0MR3     (*(volatile unsigned *)(SFR_BADDR + 0x04024))         //Match Register 3
#define rT0CCR     (*(volatile unsigned *)(SFR_BADDR + 0x04028))         //Capture Control
#define rT0CR0     (*(volatile unsigned *)(SFR_BADDR + 0x0402c))         //Capture Register 0
#define rT0CR1     (*(volatile unsigned *)(SFR_BADDR + 0x04030))         //Capture Register 1
#define rT0CR2     (*(volatile unsigned *)(SFR_BADDR + 0x04034))         //Capture Register 2
#define rT0CR3     (*(volatile unsigned *)(SFR_BADDR + 0x04038))         //Capture Register 3
#define rT0EMR     (*(volatile unsigned *)(SFR_BADDR + 0x0403c))         //External Match
#define rT0CTCR    (*(volatile unsigned *)(SFR_BADDR + 0x04070))         //Count Control

// Timer 1
#define rT1IR      (*(volatile unsigned *)(SFR_BADDR + 0x08000))         //Interrupt Register
#define rT1TCR     (*(volatile unsigned *)(SFR_BADDR + 0x08004))         //Timer Control
#define rT1TC      (*(volatile unsigned *)(SFR_BADDR + 0x08008))         //Timer Counter
#define rT1PR      (*(volatile unsigned *)(SFR_BADDR + 0x0800c))         //Prescale Register
#define rT1PC      (*(volatile unsigned *)(SFR_BADDR + 0x08010))         //Prescale Counter
#define rT1MCR     (*(volatile unsigned *)(SFR_BADDR + 0x08014))         //Match Control
#define rT1MR0     (*(volatile unsigned *)(SFR_BADDR + 0x08018))         //Match Register 0
#define rT1MR1     (*(volatile unsigned *)(SFR_BADDR + 0x0801c))         //Match Register 1
#define rT1MR2     (*(volatile unsigned *)(SFR_BADDR + 0x08020))         //Match Register 2
#define rT1MR3     (*(volatile unsigned *)(SFR_BADDR + 0x08024))         //Match Register 3
#define rT1CCR     (*(volatile unsigned *)(SFR_BADDR + 0x08028))         //Capture Control