dsp28_mcbsp.c

微机通过串口通信精确控制pwm频率和脉宽。

//
//      TMDX ALPHA RELEASE
//      Intended for product evaluation purposes
//
//###########################################################################
//
// FILE:	DSP28_McBSP.c
//
// TITLE:	DSP28 Deviec McBSP Initialization & Support Functions.
//
//###########################################################################
//
//  Ver | dd mmm yyyy | Who  | Description of changes
// =====|=============|======|===============================================
//  0.55| 06 May 2002 | L.H. | EzDSP Alpha Release
//  0.56| 20 May 2002 | L.H. | No change
//  0.57| 27 May 2002 | L.H. | No change
//###########################################################################

#include "DSP28_Device.h"

//---------------------------------------------------------------------------
// InitMcbsp: 
//---------------------------------------------------------------------------
// This function initializes the McBSP to a known state.
//
void InitMcbsp(void)
{

        

    McbspaRegs.SPCR2.all=0x0000;                        // XRST =0
    McbspaRegs.SPCR1.all=0x8000;                        // RRST =0, DLB enabled
    McbspaRegs.RCR2.all=0x0;
    McbspaRegs.RCR1.all=0x0;
    McbspaRegs.XCR2.all=0x0;
    McbspaRegs.XCR1.all=0x0;
    McbspaRegs.SRGR2.all=0x200f;                      
    McbspaRegs.SRGR1.all=0x0001;
    McbspaRegs.MCR2.all=0x0;
    McbspaRegs.MCR1.all=0x0;
    McbspaRegs.PCR1.all=0x00a00;
// Bit changes for the test  

    McbspaRegs.SPCR1.bit.RJUST =00;                    // word Rjustifed 
    McbspaRegs.SRGR2.bit.FSGM=1;                        // FSGM =1 for FSX based on write to DXR -XSR
                                                      // has to be set FWID to work!
    McbspaRegs.SRGR2.bit.FPER=29;  //McbspaRegs.SRGR2.bit.FPER=29;//确定下一镇同步信号的有效时间，即设定周期为clkg周期的29+1=30倍。频率为41.67kHZ
                                  //da采样率为FS的频率，即左右时钟的频率 
                                  //于是da的mclk频率为=8MhZ  ,mclk/samplerate=192,工作于HRM模式
    McbspaRegs.SRGR1.bit.CLKGDV =11; // set CLKGDV = 11,clkx=LOSPCP/12=15/12=1.25MHz
    McbspaRegs.SRGR1.bit.FWID =16; // set Fwidth =1      
    McbspaRegs.RCR2.bit.RCOMPAND =00;// No R/XCOMPAND 
    McbspaRegs.XCR2.bit.XCOMPAND =00;   
    McbspaRegs.XCR1.bit.XWDLEN1  =02; //发送字长16位
    McbspaRegs.PCR1.bit.CLKXP=1;
//  McBSP Reset to enable 
    McbspaRegs.SPCR2.bit.XRST =1; // enable XRST/RRST
    McbspaRegs.SPCR1.bit.RRST=1;
  wait(50) ;
    McbspaRegs.SPCR2.all |=0x00C0;
  	
}	
	
//===========================================================================
// No more.
//===========================================================================