signedadder_4.vhd

来自「四位有符号数的加法」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity signedadder_4 is
	port(adder1,adder0:in std_logic_vector(3 downto 0);
	addsub:in std_logic;
	result:out std_logic_vector (3 downto 0);
	overflow:out std_logic);
end signedadder_4;

architecture adder of signedadder_4 is
	signal temp:std_logic_vector(3 downto 0);
	begin
		process(adder1,adder0,addsub) is
			begin
				if(addsub='1') then
					temp<=adder1+adder0;
					if(adder1(3)=adder0(3) and temp(3) /= adder1(3)) then
						overflow<='1';
					else
						overflow<='0';
					end if;
				else
					temp<=adder1+ not adder0+"0001";
					if(adder1(3) /= adder0(3) and adder0(3)=temp(3)) then
						overflow<='1';
					else
						overflow<='0';
					end if;
				end if;
				result<=temp;
		end process;
end adder;