convert2_10.vhd

来自「二进制数转十进制数」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity convert2_10 is
		port(input:in std_logic_vector(3 downto 0);
			one:out std_logic_vector(7 downto 0);
			ten:out std_logic;
			Sel:out std_logic);
end convert2_10;

architecture convert of convert2_10 is
	begin
		Sel<='0';
		process(input) is
		begin
			case input is
					when "0000" =>one<="00111111"; ten<='0';
					when "0001" =>one<="00000110"; ten<='0';
					when "0010" =>one<="01011011"; ten<='0';
					when "0011" =>one<="01001111"; ten<='0';
					when "0100" =>one<="01100110"; ten<='0';
					when "0101" =>one<="01101101"; ten<='0';
					when "0110" =>one<="01111101"; ten<='0';
					when "0111" =>one<="00000111"; ten<='0';
					when "1000" =>one<="01111111"; ten<='0';
					when "1001" =>one<="01101111"; ten<='0';
					when "1010" =>one<="00111111"; ten<='1';
					when "1011" =>one<="00000110"; ten<='1';
					when "1100" =>one<="01011011"; ten<='1';
					when "1101" =>one<="01001111"; ten<='1';
					when "1110" =>one<="01100110"; ten<='1';
					when "1111" =>one<="01101101"; ten<='1';
			end case;
		end process;
end convert;