uart.c

s3c6400 ADS下官方测试程序

//////////
// Function Name : UART_SendBreak
// Function Description : This function makes SendBreak signal on selected channel
// Input : Channe [0~3]
// Output : NONE
// Version : v0.1
void UART_SendBreak(u32 cCh)
{
	
	u32 uTemp;
	volatile UART_REGS *pUartRegs;

	pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);


	uTemp = Inp32(&pUartRegs->rUCon);
	uTemp |= (1<<4);						// Send Break signal
	Outp32(&pUartRegs->rUCon,uTemp);
		
}

//////////
// Function Name : UART_EnModemINT
// Function Description : This function choose Modem Interrupt enable/disable
// Input :   cCh [ Uart channel ],    uEn [ 0 : disable     1 : enable]
// Output : NONE
// Version : v0.1
void UART_EnModemINT(u32 cCh,u32 uEn)
{
	u32 uTempReg;
	
	volatile UART_REGS *pUartRegs;

	pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);

	uTempReg = Inp32(&pUartRegs->rUmCon);
	uTempReg &= ~(1<<3);
	uTempReg |=(uEn<<3);
	Outp32(&pUartRegs->rUmCon,uTempReg);
}


//////////
// Function Name : UART_Open
// Function Description : This function set up H/W(GPIO) and initialize SFR of UART for Debugging
// Input : ch [0~4 UART channel]
// Output : g_pUartRxStr[ch] [charater type received string]
// Version : v0.1

u8 UART_Open(u8 ch) // setting H/W & initializing regiter
{


	if(ch == 0)
		g_pUartDebugRegs = UART0_BASE;
	else if(ch == 1)
		g_pUartDebugRegs = UART1_BASE;
	else if(ch == 2)
		g_pUartDebugRegs = UART2_BASE;
	else if(ch == 3)
		g_pUartDebugRegs = UART3_BASE;	


	switch(ch)
	{
		case 0 :
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_0, 2); //Uart0 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_1, 2); //Uart0 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_2, 2); //Uart0 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_3, 2); //Uart0 RTSn			
			
			if(UART_InitializeREG(UART0_BASE, &g_AUartCon[0])  == SENDBREAK)
				return SENDBREAK; // Initialize register set for Uart 0

			break;
		case 1 :
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_4, 2); //Uart1 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_5, 2); //Uart1 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_6, 2); //Uart1 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_7, 2); //Uart1 RTSn		

			if(UART_InitializeREG(UART1_BASE, &g_AUartCon[1]) == SENDBREAK)
				return SENDBREAK;

			break;
		case 2 :
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_0, 2); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_1, 2); //Uart2 TXD			

			if(UART_InitializeREG(UART2_BASE, &g_AUartCon[2]) == SENDBREAK)
				return SENDBREAK;

			break;
		case 3 :
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_2, 2); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_3, 2); //Uart2 TXD			

			if(UART_InitializeREG(UART3_BASE, &g_AUartCon[3]) == SENDBREAK)
				return SENDBREAK;

			break;
		default :
			return FALSE;
	}
	return TRUE;
}

//////////
// Function Name : UART_Open2
// Function Description : This function set up H/W(GPIO) and initialize SFR of UART for Testing
// Input : ch [0~4 UART channel]
// Output : g_pUartRxStr[ch] [charater type received string]
// Version : v0.1

u8 UART_Open2(u8 ch) // setting H/W & initializing regiter
{

	INTC_SetVectAddr(NUM_DMA0,Isr_Dma);
	if(ch == 0)
	{
		INTC_SetVectAddr(NUM_UART0,Isr_Uart0);
//		INTC_Enable(NUM_UART0);
	}
	else if(ch == 1)
	{
		INTC_SetVectAddr(NUM_UART1,Isr_Uart1);
//		INTC_Enable(NUM_UART1);
	}
	else if(ch == 2)
	{
		INTC_SetVectAddr(NUM_UART2,Isr_Uart2);
//		INTC_Enable(NUM_UART2);
	}
	else if(ch == 3)
	{
		INTC_SetVectAddr(NUM_UART3,Isr_Uart3);
//		INTC_Enable(NUM_UART3);
	}
	else
		return 0;

	switch(ch)
	{
		case 0 :
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_0, 2); //Uart0 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_1, 2); //Uart0 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_2, 2); //Uart0 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_3, 2); //Uart0 RTSn			
			
			if(UART_InitializeREG(UART0_BASE, &g_AUartCon[0])  == SENDBREAK)
				return SENDBREAK; // Initialize register set for Uart 0

			break;
		case 1 :
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_4, 2); //Uart1 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_5, 2); //Uart1 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_6, 2); //Uart1 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_7, 2); //Uart1 RTSn		

			if(UART_InitializeREG(UART1_BASE, &g_AUartCon[1]) == SENDBREAK)
				return SENDBREAK;

			break;
		case 2 :
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_0, 2); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_1, 2); //Uart2 TXD			

			if(UART_InitializeREG(UART2_BASE, &g_AUartCon[2]) == SENDBREAK)
				return SENDBREAK;

			break;
		case 3 :
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_2, 2); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_3, 2); //Uart2 TXD			

			if(UART_InitializeREG(UART3_BASE, &g_AUartCon[3]) == SENDBREAK)
				return SENDBREAK;

			break;
		default :
			return FALSE;
	}
	return TRUE;
}


//////////
// Function Name : UART_OpenModem
// Function Description : This function enable Modem Interrupt on VIC
// Input : ch [0~4 UART channel]
// Output : NONE
// Version : v0.1
void UART_OpenModem(u8 ch) 
{
	volatile UART_REGS *pUartRegs;
	u32 uTemp2;
	

	pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*ch);
	
	while (Inp32(&pUartRegs->rUfStat )& 0x3f) 	//until rx fifo count 0 (fifo clear)
	{
	(u8)(Inp32(&pUartRegs->rUrxh));
	}	

		
		Outp32(&pUartRegs->rUintSp , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));
		Outp32(&pUartRegs->rUintP , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));

		uTemp2 = Inp32(&pUartRegs->rUintM);
		uTemp2 &= ~(BIT_UART_MODEM);	
		Outp32(&pUartRegs->rUintM,uTemp2);

		INTC_Enable(NUM_UART0);
		INTC_Enable(NUM_UART1);
		INTC_Enable(NUM_UART2);
		INTC_Enable(NUM_UART3);


}



//////////
// Function Name : UART_Close
// Function Description : This function closed H/W(GPIO) and disable UART exception
// Input : ch [0~4 UART channel]
// Output : 1: success 2:fail
// Version : v0.1

u8 UART_Close(u8 ch)  // return to reset value
{
	volatile UART_REGS *pUartRegs;

	if (ch > 3) return FALSE;
	pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*ch);


	INTC_Disable(NUM_DMA0);
	
	pUartRegs->rUintM |= (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD);
	
	switch(ch)
	{
		case 0 :
			INTC_Disable(NUM_UART0);
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_4, 0); //Uart1 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_5, 0); //Uart1 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_6, 0); //Uart1 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_7, 0); //Uart1 RTSn		
	
			break;
		case 1 :
			INTC_Disable(NUM_UART1);
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_4, 0); //Uart1 RXD
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_5, 0); //Uart1 TXD			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_6, 0); //Uart1 CTSn			
			GPIO_SetFunctionEach(eGPIO_A, eGPIO_7, 0); //Uart1 RTSn		
			break;
		case 2 :
			INTC_Disable(NUM_UART2);
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_0, 0); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_1, 0); //Uart2 TXD	
			break;
		case 3 :
			INTC_Disable(NUM_UART3);
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_2, 0); //Uart2 RXD
			GPIO_SetFunctionEach(eGPIO_B, eGPIO_3, 0); //Uart2 TXD		
			break;
		default :
			printf("Can't close UARTx!! Select 0,1, or 2!!");
			return FALSE;
	}
	return TRUE;
}


//////////
// Function Name : UART_InitializeREG
// Function Description : This function set up SFR by pre-defined value 
// Input : *pUartRegs [SFR value base address]
//		 *pUartCon [Pre-defined value's base address, UART_Config]
// Output : SENDBREAK [when sendbreak signal set up]
//		    0 [nomal mode (sendbreak signal disable)]
// Version : v0.1

u32 UART_InitializeREG( UART_REGS *pUartRegs, UART_CON *pUartCon) // Initialize register set with current control set
{

	
	UART_CalcBaudrate(pUartRegs, pUartCon);

	Outp32(&pUartRegs->rUfCon , (pUartCon->cTxTrig<<6)|(pUartCon->cRxTrig<<4)|TX_FIFO_RESET|RX_FIFO_RESET
						|(pUartCon->cEnableFifo));
	
	Outp32(&pUartRegs->rUlCon , (pUartCon->cSelUartIrda<<6)|(pUartCon->cParityBit<<3)|(pUartCon->cStopBit<<2)
						|(pUartCon->cDataBit));
	Outp32(&pUartRegs->rUCon , (pUartCon->cOpClock<<10)|TX_INT_TYPE|RX_INT_TYPE|RX_ERR_INT_EN|RX_TIMEOUT_EN
						|(pUartCon->cLoopTest<<5)| (pUartCon->cSendBreakSignal<<4) |(pUartCon->cTxMode<<2)|(pUartCon->cRxMode));		
	if(pUartCon->cSendBreakSignal)
		return SENDBREAK;
//	Outp32(&pUartRegs->rUfCon , (pUartCon->cTxTrig<<6)|(pUartCon->cRxTrig<<4)|TX_FIFO_RESET|RX_FIFO_RESET
//						|(pUartCon->cEnableFifo));
	Outp32(&pUartRegs->rUmCon , (pUartCon->cRtsTrig<<5)|(pUartCon->cAfc<<4)|RTS_ACTIVE);	
	Outp32(&pUartRegs->rUintM , 0xf); // mask
	Outp32(&pUartRegs->rUintSp , 0xf); // source pending clear
	Outp32(&pUartRegs->rUintP , 0xf); // pending clear

	return 0;
	
}


//////////
// Function Name : UART_CalcBaudrate
// Function Description : This function defines UbrDiv and UdivSlot value depends on OpClock src
// Input : *pUartRegs [SFR value base address]
//		 *pUartCon [Pre-defined value's base address, UART_Config]
// Output : NONE
// Version : v0.1

void UART_CalcBaudrate( UART_REGS *pUartRegs, UART_CON *pUartCon)
{
	const u32 aSlotTable[16] = {0x0000, 0x0080, 0x0808, 0x0888, 0x2222, 0x4924, 0x4a52, 0x54aa,
				     		0x5555, 0xd555, 0xd5d5, 0xddd5, 0xdddd, 0xdfdd, 0xdfdf, 0xffdf};
	float tempDiv;
	u32 nOpClock;
	u32 nSlot;
	
	switch(pUartCon->cOpClock)
	{
		case 1 : 			
			nOpClock = g_uOpClock;
			break;// Uextclk
		case 3 :
			nOpClock = g_uOpClock;			
			break;// Epll
		case 0 :
		case 2 : // Pclk
		default : 			
			nOpClock = g_PCLK;			
			break;
	}

	tempDiv = (nOpClock/(16.*pUartCon->uBaudrate)) - 1;
	nSlot = (u32)((tempDiv - (int)tempDiv) * 16);
	Outp32(&pUartRegs->rUbrDiv , (u32)(tempDiv));
	Outp32(&pUartRegs->rUdivSlot , aSlotTable[nSlot]);	
	//printf(" div = %d, slot = 0x%x\n", (u32)(tempDiv), aSlotTable[nSlot]); 
	
}


//////////
// Function Name : Isr_Uart0~3
// Function Description : These are Interrupt Service Routine of UART which are connected to Isr_UartSub
// Input : NONE
// Output : NONE
// Version : v0.1

void __irq Isr_Uart0(void)
{		
	
	Isr_UartSub(0);	
	INTC_ClearVectAddr();
}		

void __irq Isr_Uart1(void)
{	
	Isr_UartSub(1);
	INTC_ClearVectAddr();
}

void __irq Isr_Uart2(void)
{	
	Isr_UartSub(2);
	INTC_ClearVectAddr();
}

void __irq Isr_Uart3(void)
{	
	Isr_UartSub(3);
	INTC_ClearVectAddr();	
}	


//////////
// Function Name : Isr_UartSub
// Function Description : This is Uart SubISR which checks errors and operates Tx and Rx
// Input : NONE
// Output : NONE
// Version : v0.1

void Isr_UartSub(u8 ch)
{
	u32 ErrorStatus = 0;	
	volatile UART_REGS *pUartRegs;			
	u8 tempChar;
	u32 uTemp;

	pUartRegs = ( UART_REGS *)(UART_BASE+UART_OFFSET*ch);

	
	// Check Errors 	
	if (Inp32(&pUartRegs->rUintP) & BIT_UART_ERROR)
	{
		printf("Error occured!!\n");
		uTemp = Inp32(&pUartRegs->rUintM);
		uTemp |= BIT_UART_ERROR;
		Outp32(&pUartRegs->rUintM , uTemp);
		pUartRegs->rUintM |= BIT_UART_ERROR;
//		Outp32(&pUartRegs->rUintSp , BIT_UART_ERROR|BIT_UART_RXD);
//		Outp32(&pUartRegs->rUintP , BIT_UART_ERROR|BIT_UART_RXD);
		Outp32(&pUartRegs->rUintSp , BIT_UART_ERROR);
		Outp32(&pUartRegs->rUintP , BIT_UART_ERROR);
		ErrorStatus = Inp32(&pUartRegs->rUerStat);

		switch(ErrorStatus)//to clear and check the status of register bits
		{
			case 1:
				printf("%d ch : Overrun error!\n",ch);
				break;
			case 2:
				printf("%d ch : Parity error!\n",ch);
				break;
			case 4:
				printf("%d ch : Frame error!\n",ch);
				break;
			case 6:
				printf("%d ch : Parity, Frame error!\n",ch);
				break;
			case 8:
				printf("%d ch : Breake detect\n",ch);
				break;
			case 0xa:
				printf("%d ch : Parity error & Break detect!\n",ch);
				break;
			case 0xc:
				printf("%d ch : Frame error & Breake detect\n",ch);
				break;
			case 0xe:
				printf("%d ch : Parity, Frame error & Break detect!\n",ch);
				break;
			default :
				printf("Unknown error : 0x%x\n", ErrorStatus);
				break;
		}
		
		g_AisRxDone[ch] = 1;	

		uTemp = Inp32(pUartRegs->rUintM );
		uTemp &= ~(BIT_UART_ERROR);
		Outp32(&pUartRegs->rUintM ,uTemp);
		pUartRegs->rUintM &= ~(BIT_UART_ERROR);
		
	}


	// Tx ISR	
	if (Inp32(&pUartRegs->rUintP )& BIT_UART_TXD)
	{
		uTemp = Inp32(&pUartRegs->rUintM);
		uTemp |= BIT_UART_TXD;
		Outp32(&pUartRegs->rUintM , uTemp);
//		pUartRegs->rUintM |= BIT_UART_TXD;
		Outp32(&pUartRegs->rUintSp , BIT_UART_TXD);
		Outp32(&pUartRegs->rUintP , BIT_UART_TXD);

		if (Inp32(&pUartRegs->rUfCon )& 1) // 1 : fifo enable 
		{
			// for debugging fifo 
			*g_pFifoDebug++ = ++g_uFcnt;
			*g_pFifoDebug++ = (Inp32(&pUartRegs->rUfCon)>>6)&3;