📄 uart.c
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g_uOpClock = CalcEPLL(32,1,1,0);
printf("EPLL = %dMhz\n",(g_uOpClock/1000000));
// use EPLL output clock
//SetEPLL(42, 1, 2); // Epll output - 96MHz, pll input - 12MHz
//CLK_SRC UART_SEL[13] 0:EPLL
//CLK_DIV2 UART_RATIO[19:16]
break;
case 2:
SYSC_ClkSrc(eMPLL_FOUT);
SYSC_ClkSrc(eUART_DOUTMPLL);
Delay(100);
// SYSC_CtrlCLKOUT(eCLKOUT_EPLLOUT,9);
g_uOpClock = (u32)g_MPLL/2;
// g_uOpClock = g_MPLL;
printf("MPLL = %dMhz\n",(g_uOpClock/1000000));
// use MPLL output clock
//CLK_SRC UART_SEL[13] 1:MPLL
//CLK_DIV2 UART_RATIO[19:16]
break;
default:
SYSC_ClkSrc(eMPLL_FOUT);
SYSC_ClkSrc(eUART_DOUTMPLL);
Delay(100);
// SYSC_CtrlCLKOUT(eCLKOUT_EPLLOUT,9);
g_uOpClock = (u32)g_MPLL/2;
// g_uOpClock = g_MPLL;
printf("MPLL = %dMhz\n",(g_uOpClock/1000000));
// use EPLL output clock
//SetEPLL(42, 1, 2); // Epll output - 96MHz, pll input - 12MHz
//CLK_SRC UART_SEL[13] 0:EPLL
//CLK_DIV2 UART_RATIO[19:16]
break;
}
break;
default :
pUartCon->cOpClock = 0; // PCLK
break;
}
// Select UART or IrDA 1.0
printf("\n\nSelect External Interface Type\n 1. UART[D] 2. IrDA mode\n Choose : ");
if (GetIntNum() == 2)
pUartCon->cSelUartIrda = 1; // IrDA mode
else
pUartCon->cSelUartIrda = 0; // URAT mode
// Set Baudrate
printf("\n\nType the baudrate and then change the same baudrate of host, too.\n");
printf(" Baudrate (ex 9600, 115200[D], 921600) : ");
pUartCon->uBaudrate = GetIntNum();
if ((s32)pUartCon->uBaudrate == -1)
pUartCon->uBaudrate = 115200;
// Select UART operating mode
printf("\n\nSelect Operating Mode\n 1. Interrupt[D] 2. DMA\n Choose : ");
if (GetIntNum() == 2)
{
pUartCon->cTxMode = 2; // DMA0 mode
pUartCon->cRxMode = 3; // DMA1 mode
}
else
{
pUartCon->cTxMode = 1; // Int mode
pUartCon->cRxMode = 1; // Int mode
}
// Select UART FIFO mode
printf("\n\nSelect FIFO Mode (Tx/Rx[byte])\n 1. no FIFO[D] 2. Empty/1 3. 16/8 4. 32/16 5. 48/32 \n Choose : ");
iNum = GetIntNum();
if ( (iNum>1)&&(iNum<6) )
{
pUartCon->cEnableFifo = 1;
pUartCon->cTxTrig = iNum -2;
pUartCon->cRxTrig = iNum -2;
}
else
{
pUartCon->cEnableFifo = 0;
}
// Select AFC mode enable/disable
printf("\n\nSelect AFC Mode\n 1. Disable[D] 2. Enable\n Choose : ");
if (GetIntNum() == 2)
{
pUartCon->cAfc = 1; // AFC mode enable
printf("Select nRTS trigger level(byte)\n 1. 63[D] 2. 56 3. 48 4. 40 5. 32 6. 24 7. 16 8. 8\n Choose : ");
iNum = GetIntNum();
if ( (iNum>1)&&(iNum<9) )
pUartCon->cRtsTrig = iNum -1;
else
pUartCon->cRtsTrig = 0; // default 63 byte
}
else
{
pUartCon->cAfc = 0; // AFC mode disable
}
#if 1
printf("SendBreakSignal=%d\n",pUartCon->cSendBreakSignal);
printf("Brate = %d\n, SelUartIrda = %d\n, Looptest= %d\n, Afc = %d\n, EnFiFO = %d\n, OpClk = %d\n, Databit = %d\n, Paritybit = %d\n, Stopbit = %d\n, Txmode = %d\n, TxTrig = %d\n, RxMode = %d\n, RxTrig = %d\n, RtsTrig = %d\n, SendBsig = %d\n",pUartCon->uBaudrate
,pUartCon->cSelUartIrda,
pUartCon->cLoopTest,
pUartCon->cAfc,
pUartCon->cEnableFifo,
pUartCon->cOpClock,
pUartCon->cDataBit,
pUartCon->cParityBit,
pUartCon->cStopBit,
pUartCon->cTxMode,
pUartCon->cTxTrig,
pUartCon->cRxMode,
pUartCon->cRxTrig,
pUartCon->cRtsTrig,
pUartCon->cSendBreakSignal);
#endif
return cCh;
}
//////////
// Function Name : UART_TxString
// Function Description : This function trasmits String through UART
// Input : ch [0~4 UART channel]
// str [character type string that you want to transmit, the last charater of string should be 'NULL']
// Output : NONE
// Version : v0.1
void UART_TxString(u8 ch, u8 *str) // The last character of 'str' should be NULL
{
volatile UART_REGS *pUartRegs;
volatile UART_CON *pUartCon;
u8 cTemp;
u32 uTemp2;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*ch);
pUartCon = &g_AUartCon[ch];
g_AisTxDone[ch] = 0;
g_pUartTxStr[ch] = str;
g_pFifoDebug = (u32 *)FIFO_DEBUG_BUF;
g_uFcnt = 0;
cTemp = pUartCon->cTxMode & 3;
if ( cTemp == 1 ) // interrupt mode
{
Outp32(&pUartRegs->rUintSp , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));
Outp32(&pUartRegs->rUintP , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));
uTemp2 = Inp32(&pUartRegs->rUintM);
uTemp2 &= ~(BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD);
// uTemp2 &= ~(BIT_UART_TXD);
Outp32(&pUartRegs->rUintM,uTemp2);
INTC_Enable(NUM_UART0);
INTC_Enable(NUM_UART1);
INTC_Enable(NUM_UART2);
INTC_Enable(NUM_UART3);
// pUartRegs->rUintM &= ~(BIT_UART_TXD);
}
else if ( cTemp==2 ) // dma mode
{
DMAC_InitCh(DMA0,DMA_A,&oUARTDma);
switch(ch)
{
case 0:
SYSC_SelectDMA(eSEL_UART0_0, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_A,0x0,(u32)str,0,(u32)(&pUartRegs->rUtxh),1,BYTE,strlen((const char*)str),DEMAND,MEM,DMA0_UART0_0,SINGLE,&oUARTDma);
break;
case 1:
SYSC_SelectDMA(eSEL_UART1_0, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_A,0x0,(u32)str,0,(u32)(&pUartRegs->rUtxh),1,BYTE,strlen((const char*)str),DEMAND,MEM,DMA0_UART1_0,SINGLE,&oUARTDma);
break;
case 2:
SYSC_SelectDMA(eSEL_UART2_0, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_A,0x0,(u32)str,0,(u32)(&pUartRegs->rUtxh),1,BYTE,strlen((const char*)str),DEMAND,MEM,DMA0_UART2_0,SINGLE,&oUARTDma);
break;
case 3:
SYSC_SelectDMA(eSEL_UART3_0, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_A,0x0,(u32)str,0,(u32)(&pUartRegs->rUtxh),1,BYTE,strlen((const char*)str),DEMAND,MEM,DMA0_UART3_0,SINGLE,&oUARTDma);
break;
}
INTC_Enable(NUM_DMA0);
DMACH_ClearIntPending(&oUARTDma);
DMACH_ClearErrIntPending(&oUARTDma);
DMACH_Start(&oUARTDma);
}
while(!g_AisTxDone[ch]);
// for debugging fifo
if ( (Inp32(&pUartRegs->rUfCon) & 1) && (cTemp == 1) ) // 1 : fifo enable
{
g_pFifoDebug = (u32 *)FIFO_DEBUG_BUF;
while(*g_pFifoDebug) // g_pFifoDebug address, Tx count, UfCon, g_uFcnt
printf("[0x%x,%d,0x%x,%d] ", g_pFifoDebug, *g_pFifoDebug++, *g_pFifoDebug++,*g_pFifoDebug++);
}
INTC_Disable(NUM_UART0);
INTC_Disable(NUM_UART1);
INTC_Disable(NUM_UART2);
INTC_Disable(NUM_UART3);
INTC_Disable(NUM_DMA0);
}
//////////
// Function Name : UART_RxString
// Function Description : This function receives String through UART
// Input : ch [0~4 UART channel]
// Output : g_pUartRxStr[ch] [charater type received string]
// Version : v0.1
u8* UART_RxString(u8 ch) // The last character of input string should be '\r'. simple test code
{
volatile UART_REGS *pUartRegs;
volatile UART_CON *pUartCon;
u8 cTemp;
u32 uTemp2;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*ch);
pUartCon = &g_AUartCon[ch];
g_AisRxDone[ch] = 0;
g_pUartRxStr[ch] = ( u8 *)(UART_BUF+0x200000);
g_pUartBuf = (u8 *)(UART_BUF);
g_pFifoDebug = (u32 *)FIFO_DEBUG_BUF;
g_uFcnt = 0;
while (Inp32(&pUartRegs->rUfStat )& 0x3f) //until rx fifo count 0 (fifo clear)
{
(u8)(Inp32(&pUartRegs->rUrxh));
}
cTemp = pUartCon->cRxMode & 3;
if ( cTemp == 1 ) // interrupt mode
{
Outp32(&pUartRegs->rUintSp , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));
Outp32(&pUartRegs->rUintP , (BIT_UART_MODEM|BIT_UART_TXD|BIT_UART_ERROR|BIT_UART_RXD));
uTemp2 = Inp32(&pUartRegs->rUintM);
uTemp2 &= ~(BIT_UART_ERROR|BIT_UART_RXD);
// uTemp2 &= ~(BIT_UART_RXD);
Outp32(&pUartRegs->rUintM,uTemp2);
INTC_Enable(NUM_UART0);
INTC_Enable(NUM_UART1);
INTC_Enable(NUM_UART2);
INTC_Enable(NUM_UART3);
}
else if ( cTemp == 3 ) // dma mode
{
DMAC_InitCh(DMA0,DMA_B,&oUARTDma);
switch(ch)
{
case 0:
SYSC_SelectDMA(eSEL_UART0_1, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_B,0x0,(u32)(&pUartRegs->rUrxh),1,UART_BUF,0,BYTE,DMA_BUF_LEN,HANDSHAKE,DMA0_UART0_1,MEM,SINGLE,&oUARTDma);
break;
case 1:
SYSC_SelectDMA(eSEL_UART1_1, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_B,0x0,(u32)(&pUartRegs->rUrxh),1,UART_BUF,0,BYTE,DMA_BUF_LEN,HANDSHAKE,DMA0_UART1_1,MEM,SINGLE,&oUARTDma);
break;
case 2:
SYSC_SelectDMA(eSEL_UART2_1, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_B,0x0,(u32)(&pUartRegs->rUrxh),1,UART_BUF,0,BYTE,DMA_BUF_LEN,HANDSHAKE,DMA0_UART2_1,MEM,SINGLE,&oUARTDma);
break;
case 3:
SYSC_SelectDMA(eSEL_UART3_1, 1);
// Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
DMACH_Setup(DMA_B,0x0,(u32)(&pUartRegs->rUrxh),1,UART_BUF,0,BYTE,DMA_BUF_LEN,HANDSHAKE,DMA0_UART3_1,MEM,SINGLE,&oUARTDma);
break;
}
INTC_Enable(NUM_DMA0);
DMACH_ClearIntPending(&oUARTDma);
DMACH_ClearErrIntPending(&oUARTDma);
DMACH_Start(&oUARTDma);
}
while(!UART_GetKey())
{
if(g_AisRxDone[ch])
break;
}
// for debugging fifo
if ( (Inp32(&pUartRegs->rUfCon) & 1) && (cTemp == 1) ) // 1 : fifo enable
{
g_pFifoDebug = (u32 *)FIFO_DEBUG_BUF;
while(*g_pFifoDebug)
printf("[0x%x,%d,0x%x,%d] ", g_pFifoDebug, *g_pFifoDebug++, *g_pFifoDebug++,*g_pFifoDebug++);
}
INTC_Disable(NUM_UART0);
INTC_Disable(NUM_UART1);
INTC_Disable(NUM_UART2);
INTC_Disable(NUM_UART3);
INTC_Disable(NUM_DMA0);
g_pUartRxStr[ch] = ( u8 *)(UART_BUF+0x200000);
return g_pUartRxStr[ch];
}
//////////
// Function Name : UART_WrUtxh
// Function Description : This function writes value on Utxh register
// Input : Channe [0~3] Character[which you wants to write on Utxh register]
// Output : NONE
// Version : v0.1
void UART_WrUtxh(u32 cCh,u8 cTx)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
Outp8(&pUartRegs->rUtxh,cTx);
}
//////////
// Function Name : UART_RdUrxh
// Function Description : This function reads value on Urxh register
// Input : Channe [0~3]
// Output : Urxh value
// Version : v0.1
u8 UART_RdUrxh(u32 cCh)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
return Inp8(&pUartRegs->rUrxh);
}
//////////
// Function Name : UART_RxEmpty
// Function Description : This function Hold Uart until Rx FIFO empty
// Input : Channe [0~3]
// Output : Urxh value
// Version : v0.1
void UART_RxEmpty(u32 cCh)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
while (Inp32(&pUartRegs->rUfStat )& 0x3f) //until rx fifo count 0 (fifo clear)
{
(u8)(Inp32(&pUartRegs->rUrxh));
}
}
//////////
// Function Name : UART_RdUTRSTAT
// Function Description : This function reads out UTRSTAT register
// Input : Channe [0~3]
// Output : UTRSTAT value
// Version : v0.1
u32 UART_RdUTRSTAT(u32 cCh)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
return Inp32(&pUartRegs->rUtrStat);
}
//////////
// Function Name : UART_RdUFSTAT
// Function Description : This function reads out UFSTAT register(be able to check RX FIFO cnt, full bit)
// Input : Channe [0~3]
// Output : UFSTAT value
// Version : v0.1
u32 UART_RdUFSTAT(u32 cCh)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
return Inp32(&pUartRegs->rUfStat);
}
//////////
// Function Name : UART_RdUMSTAT
// Function Description : This function reads out UMSTAT register(be able to check CTS signal bit)
// Input : Channe [0~3]
// Output : UMSTAT value
// Version : v0.1
u32 UART_RdUMSTAT(u32 cCh)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
return Inp32(&pUartRegs->rUmStat);
}
//////////
// Function Name : UART_WrRTS
// Function Description : This function choose RTS enable signal manually
// Input : RTS [RTS_inAct/RTS_Act]
// Output : NONE
// Version : v0.1
void UART_WrRTS(u32 cCh, RTS en)
{
volatile UART_REGS *pUartRegs;
pUartRegs = (volatile UART_REGS *)(UART_BASE+UART_OFFSET*cCh);
Outp32(&pUartRegs->rUmCon,en);
}
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