dma.c

s3c6400 ADS下官方测试程序

//							DMA0_UART2_0, DMA0_UART2_1, DMA0_UART3_0, DMA0_UART3_1,
//							DMA0_PCM0_TX,DMA0_PCM0_RX, DMA0_I2S0_TX, DMA0_I2S0_RX,
//							DMA0_SPI0_TX, DMA0_SPI0_RX,  DMA0_HSI_TX,   DMA0_HSI_RX,
//							[DMAC1, SDMAC1]
//							DMA1_PCM1_TX, DMA1_PCM1_RX, DMA1_I2S1_TX, DMA1_I2S1_RX,
//							DMA1_SPI1_TX,  DMA1_SPI1_RX,  DMA1_AC_PCMout, DMA1_AC_PCMin,
//							DMA1_AC_MICin, DMA1_PWM, DMA1_IrDA, DMA1_EXTERNAL
//							SDMA1_SECU_RX, SDMA1_SEXU_TX     => Only SDMAC1
//			eBurstMode	: Burst Size,  
//							SINGLE, BURST4, BURST8, BURST16, BURST32, BURST64, BURST128, BURST256
//
// Output : 	void
//			
// Version : v0.1

void DMACH_Setup(
	DMA_CH eCh, u32 uLLIAddr, u32 uSrcAddr, bool bSrcFixed, u32 uDstAddr, bool bDstFixed, DATA_SIZE eDataSz, u32 uDataCnt,
	DMA_HS_MODE eOpMode, DREQ_SRC eSrcReq, DREQ_SRC eDstReq, BURST_MODE eBurstMode, DMAC *sCh)
{
	u32 uReg;
	u32 uBurstSz;
	u32 uTrWidth;
	u32 uTCEnable;
	DMA_AHB eSrcAhb, eDstAhb;

	switch(eCh)
	{
		case DMA_A: sCh->m_uChAddr = DMA_CH0;  break;
		case DMA_B: sCh->m_uChAddr = DMA_CH1;  break;
		case DMA_C: sCh->m_uChAddr = DMA_CH2;  break;
		case DMA_D: sCh->m_uChAddr = DMA_CH3;  break;
		case DMA_E: sCh->m_uChAddr = DMA_CH4;  break;
		case DMA_F: sCh->m_uChAddr = DMA_CH5;  break;
		case DMA_G: sCh->m_uChAddr = DMA_CH6;  break;
		case DMA_H: sCh->m_uChAddr = DMA_CH7;  break;
		default : Assert(0);
	}

	Assert(uDataCnt < 0x2000000);

#if 0
	if((eSrcReq == MEM) || (eSrcReq == DMA0_OND_TX))
		eSrcAhb = AHB_MASTER1;
	else if(eSrcReq == DMA1_NAND_TX)
		eSrcAhb = AHB_MASTER2;
	else
		eSrcAhb = AHB_MASTER2;

	if((eDstReq == MEM) || (eDstReq == DMA0_OND_RX))
		eDstAhb = AHB_MASTER1;
	else if(eDstReq == DMA1_NAND_RX)
		eDstAhb = AHB_MASTER2;	
	else
		eDstAhb = AHB_MASTER2;	
#else
	if((eSrcReq == MEM) || (eSrcReq == DMA0_OND_TX)|| (eSrcReq == DMA1_EXTERNAL))
		eSrcAhb = AHB_MASTER1;
	else if(eSrcReq == DMA1_NAND_TX)
		eSrcAhb = AHB_MASTER2;
	else
		eSrcAhb = AHB_MASTER2;

	if((eDstReq == MEM) || (eDstReq == DMA0_OND_RX)|| (eDstReq == DMA1_EXTERNAL))
		eDstAhb = AHB_MASTER1;
	else if(eDstReq == DMA1_NAND_RX)
		eDstAhb = AHB_MASTER2;	
	else
		eDstAhb = AHB_MASTER2;	
#endif

	DmaChOutp32(DMA_CH_SRCADDR,	uSrcAddr);
	DmaChOutp32(DMA_CH_DSTADDR, uDstAddr);

	switch(eDataSz)
	{
		case WORD   : uTrWidth = ((2<<21)|(2<<18));break;
		case HWORD  : uTrWidth = ((1<<21)|(1<<18));break;
		case BYTE   : uTrWidth = ((0<<21)|(0<<18));break;
		default : Assert(0);
	}

	switch(eBurstMode)
	{
		case SINGLE    : uBurstSz = ((0<<15)|(0<<12));break;
		case BURST4    : uBurstSz = ((1<<15)|(1<<12));break;
		case BURST8    : uBurstSz = ((2<<15)|(2<<12));break;
		case BURST16   : uBurstSz = ((3<<15)|(3<<12));break;
		case BURST32   : uBurstSz = ((4<<15)|(4<<12));break; 
		case BURST64   : uBurstSz = ((5<<15)|(5<<12));break;
		case BURST128  : uBurstSz = ((6<<15)|(6<<12));break;
		case BURST256  : uBurstSz = ((7<<15)|(7<<12));break;
		default : Assert(0);
	}

	//Channel LLI Register Setting => not using => 0x0
	uReg =
		(uLLIAddr&~(0x3))|
		(AHB_MASTER1);		
	DmaChOutp32(DMA_CH_LLI, uReg);

	if(uLLIAddr == 0)
		uTCEnable = 1;
	else
		uTCEnable = 0;
	
      // Channel Control Register0 Setting 
      // [31]: Terminal Count interrupt 
	uReg =
		(uTCEnable<<31) |
		(bDstFixed? 0 : 1)<<27 |
		(bSrcFixed? 0 : 1)<<26 |
		(eDstAhb? 1 : 0)<<25 |
		(eSrcAhb? 1 : 0)<<24 |
		(uTrWidth) |
		(uBurstSz);
      
	DmaChOutp32(DMA_CH_CONTROL0, uReg);

      // Channel Control Register1 Setting => Transfer Size
	DmaChOutp32(DMA_CH_CONTROL1, uDataCnt);

	// Channel Configuration Register1 Setting 
#if 1
	uReg = 
		(0<<18) | // enable DMA requests
		(0<<16) | // disables locked transfers
		(1<<15) | // Teminal count interrupt enable
		(0<<14) | // Interrupt error mask
		((((eSrcReq == MEM)||(eSrcReq == DMA1_NAND_TX)||(eSrcReq == DMA0_OND_TX))? 0 : 1)<<12) |
		(((eDstReq == DMA0_OND_RX)? 1 : 0)<<10) |
		((((eDstReq == MEM)||(eDstReq == DMA1_NAND_RX)||(eDstReq == DMA0_OND_RX))? 0 : 1)<<11) |
		(((eDstReq == MEM)? 0:eDstReq)<<6) | // DstPerpheral
		(((eSrcReq == DMA0_OND_TX)? 1 : 0)<<5) |
		(((eSrcReq == MEM)? 0:eSrcReq)<<1) ; // SrcPeripheral
#else
	uReg = 
		(0<<18) | // enable DMA requests
		(0<<16) | // disables locked transfers
		(1<<15) | // Teminal count interrupt enable
		(0<<14) | // Interrupt error mask
		((((eSrcReq == MEM)||(eSrcReq == DMA1_NAND_TX)||(eSrcReq == DMA0_OND_TX)||(eSrcReq == DMA1_EXTERNAL))? 0 : 1)<<12) |
		(((eDstReq == DMA0_OND_RX)? 1 : 0)<<10) |
		((((eDstReq == MEM)||(eDstReq == DMA1_NAND_RX)||(eDstReq == DMA0_OND_RX)||(eDstReq == DMA1_EXTERNAL))? 0 : 1)<<11) |
		((((eDstReq == MEM)||(eDstReq == DMA1_EXTERNAL))? 0:eDstReq)<<6) | // DstPerpheral
		(((eSrcReq == DMA0_OND_TX)? 1 : 0)<<5) |
		((((eSrcReq == MEM)||(eSrcReq == DMA1_EXTERNAL))? 0:eSrcReq)<<1) ; // SrcPeripheral
#endif

//		(eDstReq <<6) | // DstPerpheral
//		(eSrcReq <<1) ; // SrcPeripheral

	
	DmaChOutp32(DMA_CH_CONFIG, uReg);	
}

//////////
// Function Name : DMAC_Start
// Function Description :  Enable DMA Channel
// Input : 	*sCh  : DMAC , Enabled Channel address
// Output : 	void
//			
// Version : v0.1
void DMACH_Start(DMAC *sCh)
{
	u32 uReg;
	
	uReg = DmaChInp32(DMA_CH_CONFIG);
	
	uReg |= (1<<0);                                         // Channel Enable
	DmaChOutp32(DMA_CH_CONFIG, uReg);
}

//////////
// Function Name : DMACH_AddrSetup
// Function Description : Set Source address and destination address.
// Input : 	eCh  		: Selected channel.
//			uSrcAddr		: Source Address
//			uDstAddr        : Destination Address
//
// Output : 	void
//			
// Version : v0.1

void DMACH_AddrSetup(DMA_CH eCh,  u32 uSrcAddr, u32 uDstAddr, DMAC *sCh)
{
	

	switch(eCh)
	{
		case DMA_A: sCh->m_uChAddr = DMA_CH0;  break;
		case DMA_B: sCh->m_uChAddr = DMA_CH1;  break;
		case DMA_C: sCh->m_uChAddr = DMA_CH2;  break;
		case DMA_D: sCh->m_uChAddr = DMA_CH3;  break;
		case DMA_E: sCh->m_uChAddr = DMA_CH4;  break;
		case DMA_F: sCh->m_uChAddr = DMA_CH5;  break;
		case DMA_G: sCh->m_uChAddr = DMA_CH6;  break;
		case DMA_H: sCh->m_uChAddr = DMA_CH7;  break;
		default : Assert(0);
	}

	DmaChOutp32(DMA_CH_SRCADDR,	uSrcAddr);
	DmaChOutp32(DMA_CH_DSTADDR, uDstAddr);


}


//////////
// Function Name : DMACH_ReadSrcAddr
// Function Description : Read Source Address
// Input :  Structure definition of DMAC
// Output : 	Source Address
// Version : v0.1
// added by Woojin
u32 DMACH_ReadSrcAddr(DMAC *sCh)
{
	return DmaChInp32(DMA_CH_SRCADDR);
}


//////////
// Function Name : DMACH_ReadDstAddr
// Function Description : Read Destination Address
// Input :  Structure definition of DMAC
// Output : 	Destination Address
// Version : v0.1
// added by Woojin
u32 DMACH_ReadDstAddr(DMAC *sCh)
{
	return DmaChInp32(DMA_CH_DSTADDR);
}

//added by rb1004
void DMACH_WriteSrcAddr(DMAC *sCh, u32 uSrcAddr)
{
	DmaChOutp32(DMA_CH_SRCADDR, uSrcAddr);
}

//added by rb1004
void DMACH_WriteDstAddr(DMAC *sCh, u32 uDstAddr)
{
	DmaChOutp32(DMA_CH_DSTADDR, uDstAddr);
}


//added by rb1004
void DMACH_WriteTransferSize(DMAC *sCh, u32 uSize)
{
	DmaChOutp32(DMA_CH_CONTROL1, uSize);
}


//added by rb1004
void DMACH_SoftBurstReq(DMAC *sCh, DREQ_SRC eSrcReq)
{
	DmaOutp32(DMA_SOFTBREQ,	(1<<eSrcReq));
//	while(!(DmaInp32(DMA_SOFTBREQ) & (1<<eSrcReq)));
}

//added by rb1004
void DMACH_SoftBurstLastReq(DMAC *sCh, DREQ_SRC eSrcReq)
{
	DmaOutp32(DMA_SOFTLBREQ,	(1<<eSrcReq));
	//while(!(DmaInp32(DMA_SOFTLBREQ) & (1<<eSrcReq)));
}
//////////
// Function Name : DMACH_SetTransferSize
// Function Description : This function sets TransferSize
// Input :  Transfer Size
// Output : 	NONE
// Version : v0.1
// added by Woojin
void DMACH_SetTransferSize(u32 uSize, DMAC *sCh)
{
	DmaChOutp32(DMA_CH_CONTROL1, uSize);
	
}