dma.c

s3c6400 ADS下官方测试程序

/**************************************************************************************
* 
*	Project Name : S3C6400 Validation
*
*	Copyright 2006 by Samsung Electronics, Inc.
*	All rights reserved.
*
*	Project Description :
*		This software is only for validating functions of the S3C6400.
*		Anybody can use this software without our permission.
*  
*--------------------------------------------------------------------------------------
* 
*	File Name : Dma.c
*  
*	File Description : This file implements the API functons for OneNand controller.
*
*	Author : Wonjoon Jang
*	Dept. : AP Development Team
*	Created Date : 2006/12/29
*	Version : 0.1 
* 
*	History
*	- Created(wonjoon.jang 2006/12/29)
*  
**************************************************************************************/

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <ctype.h>

#include "def.h"
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "system.h"
#include "sysc.h"
#include "dma.h"
#include "intc.h"

enum DMA_REG
{
	DMA_INT 			=  0x000, 	//[7:0] RO Interrupt status
	DMA_INTTC			=  0x004, 	//[7:0] RO Interrupt terminal count status
	DMA_INTTCC			=  0x008, 	//[7:0] WO Interrupt terminal count clear 
	DMA_INTERR			=  0x00C, 	//[7:0] RO Interrupt error status
	DMA_INTERRC		=  0x010, 	//[7:0] WO Interrupt error clear
	DMA_RAWINTTC		=  0x014, 	//[7:0] RO Raw interrupt terminal count state
	DMA_RAWINTERR	=  0x018,	//[7:0] RO Raw Interrupt error status
	DMA_ENBLDCH 		=  0x01C,	//[7:0] RO enabled channels
	DMA_SOFTBREQ		=  0x020,	//[15:0] RW Software Burst Request 16peripheral
	DMA_SOFTSREQ		=  0x024, 	//[15:0] RW Software Single Request 16peripheral
	DMA_SOFTLBREQ		=  0x028, 	//[15:0] RW Software Last Burst Request 16peripheral 
	DMA_SOFTLSREQ		=  0x02C,	//[15:0] RW Software Last Single Request 16peripheral  
	DMA_CONFIG 		=  0x030, 
									// [2] M2 AHB Master 2 endianness configuration 0=little,1=big
									// [1] M1 AHB Master 2 endianness configuration 0=little,1=big
									// [0] DMAC enable 0=disabled,1=enabled
	DMA_SYNC			=  0x034,
	DMA_CH0			=  0x100,
	DMA_CH1			=  0x120,
	DMA_CH2			=  0x140,
	DMA_CH3			=  0x160,
	DMA_CH4			=  0x180,
	DMA_CH5			=  0x1A0,
	DMA_CH6			=  0x1C0,
	DMA_CH7			=  0x1E0
};


enum DMA_CH_REG 
{
	DMA_CH_SRCADDR	= 0x00,
	DMA_CH_DSTADDR 	= 0x04,
	DMA_CH_LLI			= 0x08,
								//[31:2] Linked list item Address bits[1:0] are 0
								//[1] Undefined
								//[0] AHB master select next LLI 0=M1 1=M2
	DMA_CH_CONTROL0	= 0x0C,
	DMA_CH_CONTROL1	= 0x10,
	DMA_CH_CONFIG		= 0x14
								//[18]   RW Halt 0=enable DMA requests 1=ignore extra source DMA
								//[17]   RO  0=FIFO empty 1=FIFO has data
								//[16]   RW Lock
								//[15]   RW Terminal count interrupt mask
								//[14]   RW Interrupt error mask
								//[13:11]RW FlowCntrl
								//[9:6]  RW DestPeripheral
								//[4:1]  RW SrcPeripheral
								//[0]    RW Channel enable
};

// DMA Controller Register
#define DmaOutp32(offset, value) Outp32(sCh->m_uBaseAddr+offset, value)
#define DmaInp32(offset) Inp32(sCh->m_uBaseAddr+offset)
// DMA Channel Register
#define DmaChOutp32(offset, value) Outp32(sCh->m_uBaseAddr+sCh->m_uChAddr+offset, value)
#define DmaChInp32(offset) Inp32(sCh->m_uBaseAddr+sCh->m_uChAddr+offset)


//////////
// Function Name : DMAC_InitCh
// Function Description : This function initializes a certain DMA Controller
// Input : 	eUnit - DMA Controller Number,
//			eCh  - Used DMA Channel, DMA_A ~ DMA_H
// Output : 	void
//			
// Version : v0.1

void DMAC_InitCh(DMA_UNIT eUnit, DMA_CH eCh, DMAC *sCh)
{
	u32 x;

	if ( eUnit == DMA0 )
		sCh->m_uBaseAddr = DMA0_BASE;
	else if ( eUnit == DMA1 )
		sCh->m_uBaseAddr = DMA1_BASE;
	else if ( eUnit == SDMA0 )
		sCh->m_uBaseAddr = SDMA0_BASE;
	else if ( eUnit == SDMA1 )
		sCh->m_uBaseAddr = SDMA1_BASE;
	else
		Assert(0);

	DmaOutp32(DMA_CONFIG, 0x1);	// DMAC enabled

	x = eCh;

	DmaOutp32(DMA_INTTCC, x);		//clear pending
	DmaOutp32(DMA_INTERRC, x); 		//clear pending
}

//////////
// Function Name : DMAC_Close
// Function Description : This function close a certain DMA Controller
// Input : 	eUnit - DMA Controller Number,
//			eCh  - Used DMA Channel, DMA_A ~ DMA_H
// Output : 	void
//			
// Version : v0.1

void DMAC_Close(DMA_UNIT eUnit, DMA_CH eCh, DMAC *sCh)
{
	u32 x;

	if ( eUnit == DMA0 )
		sCh->m_uBaseAddr = DMA0_BASE;
	else if ( eUnit == DMA1 )
		sCh->m_uBaseAddr = DMA1_BASE;
	else if ( eUnit == SDMA0 )
		sCh->m_uBaseAddr = SDMA0_BASE;
	else if ( eUnit == SDMA1 )
		sCh->m_uBaseAddr = SDMA1_BASE;
	else
		Assert(0);

	DmaOutp32(DMA_CONFIG, 0x0);	// DMAC enabled

	x = eCh;

	DmaOutp32(DMA_INTTCC, x);		//clear pending
	DmaOutp32(DMA_INTERRC, x); 		//clear pending
}

//////////
// Function Name : DMAC_IsTransferDone
// Function Description : This function check the transferring datas are done.  
// Input : 	*sCh  : DMAC, Enabled Channel address
// Output : 	true   :  Transfer is done
//			false  :  Tranfser is not done
// Version : v0.1
bool DMACH_IsTransferDone(DMAC *sCh)
{
	u32 x;
	bool res;

	x = DmaChInp32(DMA_CH_CONFIG);

	if ( (x&0x1) == 0 )
		res = true;
	else
		res = false;

	return res;
}

u32 DMAC_IntStatus(DMAC *sCh)
{
	return DmaInp32(DMA_INT);
}


u32 DMACH_Configuration(DMAC *sCh)
{

	return DmaChInp32(DMA_CH_CONFIG);	
}


//////////
// Function Name : DMAC_Stop
// Function Description :  Stop DMA Operation.
// Input : 	*sCh  : DMAC , Enabled Channel address
// Output : 	void
//			
// Version : v0.1
void DMACH_Stop(DMAC *sCh)
{
	u32 uReg;
	
	uReg = DmaChInp32(DMA_CH_CONFIG);
	
	uReg &= ~(1<<0);
	DmaChOutp32(DMA_CH_CONFIG, uReg);
}

//////////
// Function Name : DMACH_GetChannelNumber
// Function Description : This function get dma channel number.
// Input : 	*sCh  : DMAC , Enabled Channel address
// Output : 	Channel status.
//			
// Version : v0.1
DMA_CH DMACH_GetChannelNumber(DMAC *sCh)
{
	u32 uRead;

	uRead = DmaInp32(DMA_INT);

	return (DMA_CH)uRead;
}

//////////
// Function Name : DMAC_ClearIntPending
// Function Description : This function clear the dma TC interrupt pending register.  
// Input : 	*sCh  : DMAC , Enabled Channel address
// Output : 	void
//			
// Version : v0.1
void DMACH_ClearIntPending(DMAC *sCh)
{
	u32 uRead;

       uRead = 	DmaInp32(DMA_INTTC);       
       
	DmaOutp32(DMA_INTTCC, uRead);	
	
}

//////////
// Function Name : DMAC_ClearErrIntPending
// Function Description : This function clear the dma Err interrupt pending register.  
// Input : 	*sCh  : DMAC , Enabled Channel address
// Output : 	void
//			
// Version : v0.1
void DMACH_ClearErrIntPending(DMAC *sCh)
{
	u32 uRead;

       uRead = 	DmaInp32(DMA_INTERR);     
       
	DmaOutp32(DMA_INTERRC, uRead);
}

//////////
// Function Name : DMAC_Setup
// Function Description : Set Channel information 
// Input : 	eCh  		: Selected channel.
//			uLLIAddr        : Linked List Item Address
//						: not using LLI => Write 0 (Default)
//			uSrcAddr		: Source Address
//			bSrcFixed	: "1" Source Fixed. "0" Source Increment. 
//			uDstAddr        : Destination Address
//			bDstFixed       : "1" Destination Fixed.  "0" Destination Increment.
//			eDataSz         : Transfer Width => BYTE/HWORD(Half-Word/WORD
//			uDataCnt		: Transfer Size [24:0] => 1 ~ 0x200_0000
//			eOpMode        : not using in pl080, DEMAND
//			eSrcReq&eDstReq : Peripheral Request Source,   Memory => MEM
//							[DMAC0, SDMAC0]
//    						DMA0_UART0_0, DMA0_UART0_1, DMA0_UART1_0, DMA0_UART1_1,