📄 dma_test.c

📁 s3c6400 ADS下官方测试程序
💻 C
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	{
		case 0: 
				INTC_Disable(NUM_DMA0);
			    	DMAC_Close(DMA0, DMA_ALL, &oDmac0);
			     	break;
               
		case 1: 
				INTC_Disable(NUM_DMA1);
				DMAC_Close(DMA1, DMA_ALL, &oDmac1);
			     	break;
		case 2: 
				INTC_Disable(NUM_SDMA0);
				DMAC_Close(SDMA0, DMA_ALL, &oDmac2);
			     	break;
		case 3: 
				INTC_Disable(NUM_SDMA1);
				DMAC_Close(SDMA1, DMA_ALL, &oDmac3);
			     	break;
			     	
		default : Assert(0);
	}
	

}

u32 DMAT_GetBurstSize(BURST_MODE eBurst)
{
	u32	uBurstSize = 0;

	switch(eBurst)
	{
		case SINGLE :
			uBurstSize = 1;
			break;
		case BURST4 :
			uBurstSize = 4;
			break;
		case BURST8 :
			uBurstSize = 8;
			break;
		case BURST16 :
			uBurstSize = 16;
			break;
		case BURST32 :
			uBurstSize = 32;
			break;
		case BURST64 :
			uBurstSize = 64;
			break;
		case BURST128 :
			uBurstSize = 128;
			break;
		case BURST256 :
			uBurstSize = 256;
			break;
	}
	return uBurstSize;
}
//////////
// Function Name : DMAT_SetLLI
// Function Description : This function set the DMA LLI feature
// Input : 	uSrcAddr - Source Address of Data
//			uDstAddr - Dest Address of Data
//			eTransferWidth - BYTE/HWORD/WORD
//			eBurst	- Burst mode
//			uDataCnts - data number which user inputs
// Output : 	None
// Version : v0.1
void DMAT_SetLLI(u32 uSrcAddr, u32 uDstAddr, DATA_SIZE eTransferWidth, BURST_MODE eBurst, u32 uDataCnts)
{
	u32	*pLLI_Base = NULL;
	u32	uLoopCnt = 0;
	u32	uOneTimeTxDataSize = 0;
	u32	uTotTxDataSize		= 0;
	u32	uMaxLoopCnt 		= 0;

	uOneTimeTxDataSize 	= eTransferWidth*DMAT_GetBurstSize(eBurst);
	uTotTxDataSize		= eTransferWidth*uDataCnts;
	uMaxLoopCnt 			= (uTotTxDataSize%uOneTimeTxDataSize == 0) ? uTotTxDataSize/uOneTimeTxDataSize : (uTotTxDataSize/uOneTimeTxDataSize + 1);

	pLLI_Base = (u32 *)uLLIBaseAddr;

	for(uLoopCnt=0 ; uLoopCnt<uMaxLoopCnt; uLoopCnt++)
	{
		*pLLI_Base++ = uSrcAddr + (uLoopCnt*uOneTimeTxDataSize);
		*pLLI_Base++ = uDstAddr + (uLoopCnt*uOneTimeTxDataSize);
		*pLLI_Base++ = (uLLIBaseAddr + ((uLoopCnt+1)*0x20));
		*pLLI_Base++ = (1<<27) | (1<<26) | (0<<25) | (0<<24) | ((eTransferWidth>>1)<<21)|((eTransferWidth>>1)<<18)|(eBurst<<15)|(eBurst<<12);
//		*pLLI_Base++ = uDataCnts;
		*pLLI_Base++ = uOneTimeTxDataSize;
		pLLI_Base += 3;
	}

	*pLLI_Base++ = uSrcAddr + (uLoopCnt*uOneTimeTxDataSize);
	*pLLI_Base++ = uDstAddr + (uLoopCnt*uOneTimeTxDataSize);
	*pLLI_Base++ = 0;				// 	Finish LLI operation
//	*pLLI_Base++ = uLLIBaseAddr;		// 	Loop DMA LLI operation
	*pLLI_Base++ = (1<<31) | (1<<27) | (1<<26) | (0<<25) | (0<<24) | ((eTransferWidth>>1)<<21)|((eTransferWidth>>1)<<18)|(eBurst<<15)|(eBurst<<12);
//	*pLLI_Base++ = uDataCnts;
	*pLLI_Base++ = uOneTimeTxDataSize;
}

//////////
// Function Name : DMAT_MemtoMemLLI
// Function Description : Memory to Memory Transfer Test
// Input : 	None
// Output :	None 
// Version : v0.1
static void DMAT_MemtoMemLLI(void)
{
	u32 i, csel, usel;
	u32 uTsize, uBurst, uCh;

	g_DmaDone=0;
	
	Disp("\nSelect DMA Controller : 0:DMA0, 1:DMA1, 2:SDMA0, 3:SDMA1	: ");
	csel=GetIntNum();
	Disp("\n");

	switch(csel)
	{
		case 0: 
				Disp("Selected DMAC 0 ..... \n");
			     	DMAC_InitCh(DMA0, DMA_ALL, &oDmac0);
				INTC_SetVectAddr(NUM_DMA0,  Dma0Done);
				INTC_Enable(NUM_DMA0);
			     	break;
               
		case 1: 
				Disp("Selected DMAC 1 ..... \n");
			     	DMAC_InitCh(DMA1, DMA_ALL, &oDmac1);
				INTC_SetVectAddr(NUM_DMA1,  Dma1Done);
				INTC_Enable(NUM_DMA1);
			     	break;
		case 2: 
				Disp("Selected SDMAC 0 ..... \n");
			     	DMAC_InitCh(SDMA0, DMA_ALL, &oDmac2);
				INTC_SetVectAddr(NUM_SDMA0, Sdma0Done );
				INTC_Enable(NUM_SDMA0);
			     	break;
		case 3: 
				Disp("Selected SDMAC 1 ..... \n");
			     	DMAC_InitCh(SDMA1, DMA_ALL, &oDmac3);
				INTC_SetVectAddr(NUM_SDMA1, Sdma1Done);
				INTC_Enable(NUM_SDMA1);
			     	break;
			     	
		default : Assert(0);
	}
       

       Disp("\nSelect Channel : 0:CH0, 1:CH1, 2:CH2, 3:CH3, 4:CH4, 5:CH5, 6:CH6, 7:CH7	: ");
	usel=GetIntNum();
	Disp("\n");

	switch(usel)
	{
		case 0: 
				uCh= DMA_A;
			     	break;             
		case 1: 
				uCh= DMA_B;
			     	break;
		case 2: 
				uCh= DMA_C;
			     	break;
		case 3: 
				uCh = DMA_D;
			     	break;	     	
		case 4: 
				uCh = DMA_E;
			     	break;
		case 5: 
				uCh = DMA_F;
			     	break;
		case 6: 
				uCh = DMA_G;
			     	break;
		case 7: 
				uCh = DMA_H;
			     	break;				
			     	
		default : Assert(0);
	}



	Disp("\nSelect Transfer Width : 0:BYTE, 1:HWORD, 2:WORD	: ");
	usel=GetIntNum();
	Disp("\n");

       switch(usel)
	{
		case 0: 
				uTsize = BYTE;
			     	break;
               
		case 1: 
				uTsize = HWORD;
			     	break;
		case 2: 
				uTsize = WORD;
			     	break;
					     	
		default : Assert(0);
	}

       Disp("\nSelect Burst Size : 0:SINGLE, 1:BURST4, 2:BURST8, 3:BURST16, 4:BURST32, 5:BURST64, 6:BURST128, 7:BURST256	: ");
	usel=GetIntNum();
	Disp("\n");

	switch(usel)
	{
		case 0: 
				uBurst = SINGLE;
			     	break;             
		case 1: 
				uBurst = BURST4;
			     	break;
		case 2: 
				uBurst = BURST8;
			     	break;
		case 3: 
				uBurst = BURST16;
			     	break;	     	
		case 4: 
				uBurst = BURST32;
			     	break;
		case 5: 
				uBurst = BURST64;
			     	break;
		case 6: 
				uBurst = BURST128;
			     	break;
		case 7: 
				uBurst = BURST256;
			     	break;				
			     	
		default : Assert(0);
	}
  
       Disp("\nSelect Transfer Size [1~0x200_0000] :   ");
	uDataCnts=GetIntNum();
	Disp("\n");

	// 0. Clear the rx/tx buf.
	for (i = 0; i<(uDataCnts*uTsize+16); i++)
	{
		*(u8 *)(uRxBuffAddr+i) = 0;
		*(u8 *)(uTxBuffAddr+i) = 0;
	}
	
	// 1. Set up the tx buf.
	for (i = 0; i<uDataCnts*uTsize; i++)
		*(u8 *)(uTxBuffAddr+i) = (u8)(i+2)%0xff;

	DMAT_SetLLI(uTxBuffAddr, uRxBuffAddr, (DATA_SIZE)uTsize, (BURST_MODE)uBurst, uDataCnts);
	Disp("LLI Table Composition complete... now, DMA Start!!\n");
	switch(csel)
	{
		case 0 :
		        // Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
			DMACH_Setup((DMA_CH)uCh, uLLIBaseAddr+0x20, uTxBuffAddr, 0, uRxBuffAddr, 0, (DATA_SIZE)uTsize, uDataCnts, DEMAND, MEM, MEM, (BURST_MODE)uBurst, &oDmac0);
			DMACH_Start(&oDmac0);
			break;
		case 1 :
		        // Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
			DMACH_Setup((DMA_CH)uCh, uLLIBaseAddr+0x20, uTxBuffAddr, 0, uRxBuffAddr, 0, (DATA_SIZE)uTsize, uDataCnts, DEMAND, MEM, MEM, (BURST_MODE)uBurst, &oDmac1);
			DMACH_Start(&oDmac1);
			break;
		case 2 :
		        // Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
			DMACH_Setup((DMA_CH)uCh, uLLIBaseAddr+0x20, uTxBuffAddr, 0, uRxBuffAddr, 0, (DATA_SIZE)uTsize, uDataCnts, DEMAND, MEM, MEM, (BURST_MODE)uBurst, &oDmac2);
			DMACH_Start(&oDmac2);
			break;
		case 3 :
		        // Channel, LLI_Address, SrcAddr, Src Type, DstAddr, Dst Type, Transfer Width, Transfer Size, OpMode(DEMAND), Src Req, Dst Req, Burst
			DMACH_Setup((DMA_CH)uCh, uLLIBaseAddr+0x20, uTxBuffAddr, 0, uRxBuffAddr, 0, (DATA_SIZE)uTsize, uDataCnts, DEMAND, MEM, MEM, (BURST_MODE)uBurst, &oDmac3);
			DMACH_Start(&oDmac3);
			break;
		default :
			Assert(0);
	}

	while(g_DmaDone==0);								// Int.
	//while (!DMAC_IsTransferDone(&oDmac0));			// Polling

	if (CompareDMA(uTxBuffAddr, uRxBuffAddr, (DATA_SIZE)uTsize, uDataCnts))
		Disp(" >> Test Tx&Rx -> Ok << \n");
	else
	{
		Disp(" >>*** Tx-data & Rx-data mismatch ***<< \n");
	}


	switch(csel)
	{
		case 0: 
				INTC_Disable(NUM_DMA0);
			    	DMAC_Close(DMA0, DMA_ALL, &oDmac0);
			     	break;
               
		case 1: 
				INTC_Disable(NUM_DMA1);
				DMAC_Close(DMA1, DMA_ALL, &oDmac1);
			     	break;
		case 2: 
				INTC_Disable(NUM_SDMA0);
				DMAC_Close(SDMA0, DMA_ALL, &oDmac2);
			     	break;
		case 3: 
				INTC_Disable(NUM_SDMA1);
				DMAC_Close(SDMA1, DMA_ALL, &oDmac3);
			     	break;
			     	
		default : Assert(0);
	}
}

//////////
// Function Name : DMAT_SoftReq
// Function Description : DMA Software Request Test
// Input : 	None
// Output :	None 
// Version : v0.1
static void DMAT_SoftReq(void)
{
	u32 i, csel;

	g_DmaDone=0;
	
	Disp("\nSelect DMA Controller : 0:DMA0, 1:DMA1, 2:SDMA0, 3:SDMA1	: ");
	csel=GetIntNum();
	Disp("\n");

	switch(csel)
	{
		case 0: 
				Disp("Selected DMAC 0 ..... \n");
				SYSC_SelectDMA(eSEL_I2S0_TX, 1);
				
			     	DMAC_InitCh(DMA0, DMA_ALL, &oDmac0);
				INTC_SetVectAddr(NUM_DMA0,  Dma0Done);
				INTC_Enable(NUM_DMA0);
			     	break;
               
		case 1: 
				Disp("Selected DMAC 1 ..... \n");
				SYSC_SelectDMA(eSEL_PWM, 1);
				
			     	DMAC_InitCh(DMA1, DMA_ALL, &oDmac1);
				INTC_SetVectAddr(NUM_DMA1,  Dma1Done);
				INTC_Enable(NUM_DMA1);

				DMACH_ClearErrIntPending(&oDmac1);
			  	DMACH_ClearIntPending(&oDmac1);
				
			     	break;
		case 2: 
				Disp("Selected SDMAC 0 ..... \n");
				SYSC_SelectDMA(eSEL_I2S0_TX, 0);
				
			     	DMAC_InitCh(SDMA0, DMA_ALL, &oDmac2);
				INTC_SetVectAddr(NUM_SDMA0, Sdma0Done );
				INTC_Enable(NUM_SDMA0);
			     	break;
		case 3: 
				Disp("Selected SDMAC 1 ..... \n");
				SYSC_SelectDMA(eSEL_PWM, 0);
				
			     	DMAC_InitCh(SDMA1, DMA_ALL, &oDmac3);
				INTC_SetVectAddr(NUM_SDMA1, Sdma1Done);
				INTC_Enable(NUM_SDMA1);
			     	break;
			     	
		default : Assert(0);
	}
       
#if 0
       Disp("\nSelect Transfer Size [1~0x200_0000] :   ");
	uDataCnts=GetIntNum();
	Disp("\n");
#else
	uDataCnts=100;
#endif

	// 0. Clear the rx/tx buf.
	for (i = 0; i<(uDataCnts*WORD+16); i++)
	{
		*(u8 *)(uRxBuffAddr+i) = 0;
		*(u8 *)(uTxBuffAddr+i) = 0;
	}
	
	// 1. Set up the tx buf.
	for (i = 0; i<uDataCnts*WORD; i++)
		*(u8 *)(uTxBuffAddr+i) = (u8)(i+2)%0xff;

	uRxBuffAddr = 0x7f006010;
//	Disp("uRxBuffAddr:0x%x\n", uRxBuffAddr);

	switch(csel)
	{
		case 0: 	 // Channel Set-up
				DMACH_Setup((DMA_CH)DMA_A, 0x0, uTxBuffAddr, 0, 0x7F002010, 1, (DATA_SIZE)WORD, 1, DEMAND, MEM, DMA0_I2S0_TX, (BURST_MODE)SINGLE, &oDmac0);	
			        // Enable DMA
				DMACH_Start(&oDmac0);

				Disp("DMA doesn't send request not yet. Now sending...\n");
				Getc();
				DMACH_SoftBurstReq(&oDmac0, DMA0_I2S0_TX);	// SoftWare Burst Request to DMA0_I2S0_TX source
				Disp("DMA request was sent.\n");

			     	break;               
		case 1: 
				DMACH_Setup((DMA_CH)DMA_A, 0x0, uTxBuffAddr, 0, 0x7f006010, 1, (DATA_SIZE)WORD, 1, DEMAND, MEM, DMA1_PWM, (BURST_MODE)SINGLE, &oDmac1);
			        // Enable DMA
				DMACH_Start(&oDmac1);

				Disp("DMA doesn't send request not yet. Now sending...\n");
				Getc();
				DMACH_SoftBurstReq(&oDmac1, DMA1_PWM);	// SoftWare Burst Request to DMA1_PWM source
				Disp("DMA request was sent.\n");

			     	break;
		case 2: 
				DMACH_Setup((DMA_CH)DMA_A, 0x0, uTxBuffAddr, 0, 0x7F002010, 1, (DATA_SIZE)WORD, 1, DEMAND, MEM, DMA0_I2S0_TX, (BURST_MODE)SINGLE, &oDmac2);	
			        // Enable DMA
				DMACH_Start(&oDmac2);

				Disp("DMA doesn't send request not yet. Now sending...\n");
				Getc();
				DMACH_SoftBurstReq(&oDmac2, DMA0_I2S0_TX);	// SoftWare Burst Request to DMA0_I2S0_TX source
				Disp("DMA request was sent.\n");

			     	break;
		case 3: 
				DMACH_Setup((DMA_CH)DMA_A, 0x0, uTxBuffAddr, 0, 0x7f006010, 1, (DATA_SIZE)WORD, 1, DEMAND, MEM, DMA1_PWM, (BURST_MODE)SINGLE, &oDmac3);
			        // Enable DMA
				DMACH_Start(&oDmac3);

				Disp("DMA doesn't send request not yet. Now sending...\n");
				Getc();
				DMACH_SoftBurstReq(&oDmac3, DMA1_PWM);	// SoftWare Burst Request to DMA1_PWM source
				Disp("DMA request was sent.\n");
			     	break;
			     	
		default : Assert(0);
	}	
        
	while(g_DmaDone==0);								// Int.
#if 0
	if (CompareDMA(uTxBuffAddr, uRxBuffAddr, (DATA_SIZE)WORD, uDataCnts))
		Disp(" >> Test Tx&Rx -> Ok << \n");
	else
	{
		Disp(" >>*** Tx-data & Rx-data mismatch ***<< \n");
	}
#else
	Disp("SoftDMA request was received.\n");
#endif

	switch(csel)
	{
		case 0: 
				INTC_Disable(NUM_DMA0);
			    	DMAC_Close(DMA0, DMA_ALL, &oDmac0);
			     	break;
               
		case 1: 
				INTC_Disable(NUM_DMA1);
				DMAC_Close(DMA1, DMA_ALL, &oDmac1);
			     	break;
		case 2: 
				INTC_Disable(NUM_SDMA0);
				DMAC_Close(SDMA0, DMA_ALL, &oDmac2);
			     	break;
		case 3: 
				INTC_Disable(NUM_SDMA1);
				DMAC_Close(SDMA1, DMA_ALL, &oDmac3);
			     	break;
			     	
		default : Assert(0);
	}	
}

//////////
// Function Name : DMAT_WorstCase
// Function Description : DMA Worst Case Test
// Input : 	None
// Output :	None 
// Version : v0.1
static void DMAT_WorstCase(void)
{
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