📄 sblock_test.c
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Disp("_IV_1st_ENC Success..\n");
}
else
{
Disp("AES");
Disp("_IV_1st_ENC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("AES_CTR");
Disp("_IV_1st_ENC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
// Decryption
//SBLK_Init(AES, CBC, DEC);
SBLK_Init_Test2(AES, CTR, ENC);
SBLK_SetFifo(8, 4, 8, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF, 8);
while(!SBLK_IsFifoTransDone());
// Intermediate CTR Back-up
Copy(0x7D1000B0, MID_BUF+0x20, 4);
SBLK_GetDataFromTxFifo(INPUT_BUF, 8);
//Copy((u32)uAesPlainText, GOLDEN_BUF, 16);
uRet = Compare(INPUT_BUF, GOLDEN_BUF1, 8);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("AES_");
Disp("_IV_1st_DEC Success..\n");
}
else
{
Disp("AES");
Disp("_IV_1st_DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("AES_CTR");
Disp("_IV_1st_DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
// 2nd Encryption
SBLK_Init_Test2(AES, CTR, ENC);
Copy(MID_BUF, 0x7D1000B0, 4); // Intermediate IV
SBLK_SetFifo(8, 4, 8, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo((u32)uAesPlainText+0x20, 8);
while(!SBLK_IsFifoTransDone());
// Intermediate IV Back-up
SBLK_GetDataFromTxFifo(OUTPUT_BUF+0x20, 8);
//Copy((u32)uAesCipherText[CBC], GOLDEN_BUF, 16);
uRet = Compare(OUTPUT_BUF+0x20, GOLDEN_BUF+0x20, 8);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("AES_");
Disp("_IV_2nd_ENC Success..\n");
}
else
{
Disp("AES");
Disp("_IV_2nd_ENC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("AES_CTR");
Disp("_IV_2nd_ENC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
// 2nd Decryption
// Decryption
SBLK_Init_Test2(AES, CTR, ENC);
Copy(MID_BUF+0x20, 0x7D1000B0, 4); // Intermediate IV
SBLK_SetFifo(8, 4, 8, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF+0x20, 8);
while(!SBLK_IsFifoTransDone());
SBLK_GetDataFromTxFifo(INPUT_BUF+0x20, 8);
//Copy((u32)uAesPlainText, GOLDEN_BUF, 16);
uRet = Compare(INPUT_BUF+0x20, GOLDEN_BUF1+0x20, 8);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("AES_");
Disp("_IV_2nd_DEC Success..\n");
}
else
{
Disp("AES");
Disp("_IV_2nd_DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("AES_CTR");
Disp("_IV_2nd_DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
}
void Test_AES_CONT_DEC(eFunction_Test eTest, oFunctionT_AutoVar oAutoVar)
{
u32 uRet;
//g_sblock_err=0;
if(eTest == eTest_Manual)
{
printf("[SBLOCK - AES Continuos Decryption Test]\n");
}
else
{
}
Copy((u32)uAesCipherText, GOLDEN_BUF, 16);
Copy((u32)uAesPlainText, GOLDEN_BUF1, 16);
///////////////////////
//ECB 128bit Decryption
SBLK_Init(AES, ECB, DEC);
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF, 4);
while(((Inp32(0x7D800000)>>16)&0xFFFF)==0x4); // Tx FIFO 1Word Read Done From AES
SBLK_GetDataFromTxFifo(INPUT_BUF, 4);
Outp32(0x7D400000, 0x4);
Outp32(0x7D800000, 0x4); // FIFO Reset
uRet = Compare(INPUT_BUF, GOLDEN_BUF1, 4);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("ECB 128bit DEC Success..\n");
}
else
{
Disp("ECB 128bit DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
printf("ECB 128bit DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
////////////////////////////////
//ECB 128bit Continuous Decryption
Outp32(0x7D100000, 0x118); // 128Bit ECB Continuous Decryption.
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF+0x10, 12);
while(((Inp32(0x7D800000)>>25)&0xFF)==0x1); // Transfer Done Polling
SBLK_GetDataFromTxFifo(INPUT_BUF+0x10, 12);
uRet = Compare(INPUT_BUF+0x10, GOLDEN_BUF1+0x10, 12);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("ECB 128bit Cont. DEC Success..\n");
}
else
{
Disp("ECB 128bit Cont. DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
printf("ECB 128bit Cont. DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
//////////////////////////////////////////////
Copy((u32)uAesCipherText+0x40, GOLDEN_BUF, 16);
///////////////////////////////////////
//CBC 128bit Decryption
SBLK_Init(AES, CBC, DEC);
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF, 4);
while(((Inp32(0x7D800000)>>16)&0xFFFF)==0x4); // Tx FIFO 1Word Read Done From AES
Copy(0x7D1000A0, MID_BUF, 4); // Intermedate IV Backup
SBLK_GetDataFromTxFifo(INPUT_BUF, 4);
Outp32(0x7D400000, 0x4);
Outp32(0x7D800000, 0x4); // FIFO Reset
uRet = Compare(INPUT_BUF, GOLDEN_BUF1, 4);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("CBC 128bit DEC Success..\n");
}
else
{
Disp("CBC 128bit DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("CBC 128bit DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
///////////////////////////////////////
//ECB 128bit Continuous Decryption
Outp32(0x7D100000, 0x128); // 128Bit CBC Continuous Decryption.
Copy(MID_BUF, 0x7D1000A0, 4); // Load IV
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF+0x10, 12);
while(((Inp32(0x7D800000)>>25)&0xFF)==0x1); // Transfer Done Polling
SBLK_GetDataFromTxFifo(INPUT_BUF+0x10, 12);
uRet = Compare(INPUT_BUF+0x10, GOLDEN_BUF1+0x10, 12);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("CBC 128bit Cont. DEC Success..\n");
}
else
{
Disp("CBC 128bit Cont. DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("CBC 128bit Cont. DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
//////////////////////////////////////////////
Copy((u32)uAesCipherText+0x80, GOLDEN_BUF, 16);
//CBC 128bit Decryption
SBLK_Init(AES, CTR, ENC);
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF, 4);
while(((Inp32(0x7D800000)>>16)&0xFFFF)==0x4); // Tx FIFO 1Word Read Done From AES
Copy(0x7D1000B0, MID_BUF, 4); // Intermedate CTR Backup
SBLK_GetDataFromTxFifo(INPUT_BUF, 4);
Outp32(0x7D400000, 0x4);
Outp32(0x7D800000, 0x4); // FIFO Reset
uRet = Compare(INPUT_BUF, GOLDEN_BUF1, 4);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("CTR 128bit DEC Success..\n");
}
else
{
Disp("CTR 128bit DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("CTR 128bit DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
//ECB 128bit Continuous Decryption
Outp32(0x7D100000, 0x130); // 128Bit CBC Continuous Decryption.
Copy(MID_BUF, 0x7D1000B0, 4); // Load CTR
SBLK_SetFifo(0xc, 4, 0xc, 4, LASTBYTE_1ST);
SBLK_StartFifo();
SBLK_PutDataToRxFifo(GOLDEN_BUF+0x10, 12);
while(((Inp32(0x7D800000)>>25)&0xFF)==0x1); // Transfer Done Polling
SBLK_GetDataFromTxFifo(INPUT_BUF+0x10, 12);
uRet = Compare(INPUT_BUF+0x10, GOLDEN_BUF1+0x10, 12);
if(eTest == eTest_Manual)
{
if (uRet)
{
Disp("CTR 128bit Cont. DEC Success..\n");
}
else
{
Disp("CTR 128bit Cont. DEC Failed..\n");
}
}
else
{
if(uRet == false)
{
Disp("CTR 128bit Cont. DEC Failed..\n");
g_sblock_err =1;
UART_Getc();
}
}
}
#if 0
void Test_AES_Temp(void)
{
u32 uRet, i;
// Encryption
//SBLK_Init(AES, CBC, ENC);
SBLK_Init_Test(AES, eAesOperMode, ENC);
for (i=0; i<4; i++)
{
SBLK_PutDataToInReg((u32)uAesPlainText+i*4*4, 4, LASTBYTE_1ST); // LASTBYTE => not affect to AES operating
SBLK_StartByManual();
while(!SBLK_IsOutputReady());
SBLK_GetDataFromOutReg(OUTPUT_BUF+i*4*4, 4);
}
// Decryption
if (eAesOperMode == CTR)
SBLK_Init_Test(AES, eAesOperMode, ENC);
else
SBLK_Init_Test(AES, eAesOperMode, DEC);
for (i=0; i<4; i++)
{
SBLK_PutDataToInReg(OUTPUT_BUF+i*4*4, 4, LASTBYTE_1ST);
SBLK_StartByManual();
while(!SBLK_IsOutputReady());
SBLK_GetDataFromOutReg(GOLDEN_BUF+i*4*4, 4);
}
Copy((u32)uAesPlainText, INPUT_BUF, 16); // Original Data
uRet = Compare(INPUT_BUF, GOLDEN_BUF, 16); // Original ->ENC->DEC
if (uRet)
{
Disp("AES_");
DispOperMode(eAesOperMode);
Disp("_CPU Success..\n");
}
else
{
Disp("AES");
DispOperMode(eAesOperMode);
Disp("_CPU Failed..\n");
}
}
void Test_DES_Temp(void)
{
u32 uRet, i;
// Encryption
SBLK_Init_Test(DES, eDesOperMode, ENC);
for (i=0; i<8; i++)
{
SBLK_PutDataToInReg((u32)uDesPlainText+i*4*2, 2, LASTBYTE_1ST);
SBLK_StartByManual();
while(!SBLK_IsOutputReady());
SBLK_GetDataFromOutReg(OUTPUT_BUF+i*4*2, 2);
}
// Decryption
SBLK_Init_Test(DES, eDesOperMode, DEC);
for (i=0; i<8; i++)
{
SBLK_PutDataToInReg(OUTPUT_BUF+i*4*2, 2, LASTBYTE_1ST);
SBLK_StartByManual();
while(!SBLK_IsOutputReady());
SBLK_GetDataFromOutReg(GOLDEN_BUF+i*4*2, 2);
}
Copy((u32)uDesPlainText, INPUT_BUF, 16);
uRet = Compare(INPUT_BUF, GOLDEN_BUF, 16);
if (uRet)
{
Disp("DES_");
DispOperMode(eDesOperMode);
Disp("_CPU_(TDES)Success..\n");
}
else
{
Disp("DES");
DispOperMode(eDesOperMode);
Disp("_CPU_(TDES) Failed..\n");
}
}
void Temp(void)
{
u32 uRet,i;
SBLK_Init(HASH, SHA1, ENC);
//SHA1 - #0
/*
for(i=0; i<7; i++){
SBLK_PutDataToInReg((u32)uSha1PlainText16, 16, LASTBYTE_4TH);
}
SBLK_PutDataToInReg((u32)uSha1PlainText16, 9, LASTBYTE_4TH); // bfb94b76, 5f566e1b
*/
SBLK_PutDataToInReg((u32)uSha1PlainText121, 25, LASTBYTE_4TH);
while(!SBLK_IsOutputReady());
SBLK_GetDataFromOutReg(OUTPUT_BUF, 5);
Copy((u32)uSha1CipherText1, GOLDEN_BUF, 5);
uRet = Compare(OUTPUT_BUF, GOLDEN_BUF, 5);
if (uRet)
{
Disp("HASH_SHA1_CPU 121 \n");
}
else
{
Disp("HASH_SHA1_CPU 121 \n");
}
Disp(" \n");
}
void Temp3(void)
{
u32 uRet, i ;
SBLK_Init(HASH, SHA1, ENC);
//SBLK_SetFifo(0x79, 0x30010, 5, 0x10, LASTBYTE_4TH);
SBLK_SetFifo(0x79, 0x30010, 5, 0x10, LASTBYTE_4TH);
SBLK_StartFifo();
for(i=0;i<6;i++){
//Wait Write Enable...
SBLK_PutDataToRxFifo((u32)uSha1PlainText16, 16);
}
SBLK_PutDataToRxFifo((u32)uSha1PlainText16, 16);
SBLK_PutDataToRxFifo((u32)uSha1PlainText16, 9);
while(!SBLK_IsFifoTransDone());
SBLK_GetDataFromTxFifo(OUTPUT_BUF, 5);
Copy((u32)uSha1CipherText16, GOLDEN_BUF, 5);
uRet = Compare(OUTPUT_BUF, GOLDEN_BUF, 5);
if (uRet)
{
Disp("HASH_");
DispOperMode(eHashOperMode);
if (eHashOperMode == HMAC)
Disp("_FIFO 19 Success..\n");
else if (eHashOperMode == SHA1)
Disp("_FIFO 16 Success..\n");
}
else
{
Disp("HASH_");
DispOperMode(eHashOperMode);
if (eHashOperMode == HMAC)
Disp("_FIFO 19 Failed..\n");
else if (eHashOperMode == SHA1)
Disp("_FIFO 16 Failed..\n");
}
}
#endif
#if 0
void SBlock_AutoT(void)
{
u32 usel;
printf("\n[SBLOCK Test]\n");
///////////////////////////////////////
///////// AES Test ///////////////////
for(usel=1;usel<4;usel++)
{
if (usel == 1) eAesOperMode = ECB;
else if (usel == 2) eAesOperMode = CBC;
else if (usel == 3) eAesOperMode = CTR;
Test_AES_CPU();
Test_AES_FIFO();
Test_AES_DMA();
}
Test_CBC_IV_FIFO();
Test_CTR_Counter();
Test_CTR_ICTR_FIFO();
Test_AES_CONT_DEC();
///////////////////////////////////////
///////// DES Test ///////////////////
for(usel=1;usel<3;usel++)
{
if (usel == 1) eDesOperMode = ECB;
else if (usel == 2) eDesOperMode = CBC;
Test_DES_CPU();
Test_DES_FIFO();
Test_DES_DMA();
}
///////////////////////////////////////
///////// HASH Test ///////////////////
for(usel=1;usel<3;usel++)
{
if (usel == 1) eHashOperMode = HMAC;
else if (usel == 2) eHashOperMode = SHA1;
Test_HASH_CPU();
Test_HASH_FIFO();
Test_HASH_DMA();
}
Test_HASH_CPU_Added();
Test_SHA1_INTERMEDIATE()⌨️ 快捷键说明
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