📄 sblock.c
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SBLK_GetAvailableRxFifoSize(&uInputSize);
if (uInputSize >= uRemainedSize)
{
uInputSize = uRemainedSize;
uRemainedSize = 0;
}
else
{
uRemainedSize -= uInputSize;
}
for(i=0; i<uInputSize; i++)
Outp32(rFIFO_RX_WR_BUF, *pSrcAddr++);
}
}
//////////
// Function Name : SBLK_GetDataFromTxFifo
// Function Description : This function get data from Tx FIFO to destination address.
// Input : uDstAddr, uSize
// Output : NONE
// Version :
void SBLK_GetDataFromTxFifo(u32 uDstAddr, u32 uSize)
{
u32 i;
u32 *uPtrSrc, *uPtrDst;
uPtrSrc = (u32 *)rFIFO_TX_RD_BUF;
uPtrDst = (u32 *)uDstAddr;
for(i=0; i<uSize; i++)
*uPtrDst++ = *uPtrSrc++;
}
//////////
// Function Name : SBLK_IsFifoTransDone
// Function Description : This function read "Done" field of the FIFO Tx Control Register.
// Input : NONE
// Output : true , false
// Version :
bool SBLK_IsFifoTransDone(void)
{
u32 uRead;//, uRead0;
//Delay(10); // printf巩 火涝矫 鞘夸 窃.
uRead=Inp32(rFIFO_TX_CTRL);
//uRead0=Inp32(rFIFO_RX_CTRL); // For Test
//printf("rFIFO_RX_CTRL : 0x%x\n", uRead); // Test 3.17
//printf("rDES_RX_CTRL : 0x%x\n", Inp32(0x7D200000));
//For Test
//SBLK_DispFifoRxCtrl(uRead0);
//SBLK_DispFifoTxCtrl(uRead);
if((uRead>>25)&1)
return true;
else
return false;
}
//////////
// Function Name : SBLK_ClearIntPending
// Function Description : This function clear int. pending of the SDMA1 Int.
// Input : uTXnRX ( 1: Tx, 0: Rx)
// Output : NONE
// Version :
void SBLK_ClearIntPending(u32 uTXnRX)
{
//u32 uRead;
if(uTXnRX == 1)
{
//uRead = (1<<6);
DMACH_ClearIntPending(&oSdma1_TX);
}
else if (uTXnRX == 0)
{
//uRead = (1<<7);
DMACH_ClearIntPending(&oSdma1_RX);
}
//Outp32(0x7DC00008, uRead);
}
//////////
// Function Name : SBLK_ClearIntPending
// Function Description : This function set SDMA1
// Input : uRxSrcAddr,uRxSize,uTxDstAddr,uTxSize
// Output : NONE
// Version :
void SBLK_SetSDMA(u32 uRxSrcAddr, u32 uRxSize, u32 uTxDstAddr, u32 uTxSize)
{
u32 uReg;
if (!(uRxSize%4)) uReg = 2<<1;
else uReg = 0<<1;
if (!(uTxSize%4)) uReg |= 2<<5;
else uReg |= 0<<5;
Outp32(rDNI_CFG, 0xFFFFFF11|uReg);
// Secure DMA input Selection
SYSC_SelectDMA(eSEL_SECU_RX, 0); // Secure Rx "SDMA1"
SYSC_SelectDMA(eSEL_SECU_TX, 0); // Secure Tx "SDMA1"
DMAC_InitCh(SDMA1, DMA_G, &oSdma1_RX); // SDMA1 Initialize
DMAC_InitCh(SDMA1, DMA_H, &oSdma1_TX);
Outp32(0x7DC00034, 0x0); // SDMA1 DMA_SYNC
// Rx Source Setting - using Channel 6 ( You can select any channel 0 to 7)
// eChannel, LLI, SrcAddr, SrcFixed, DestAddr, DstFixed, eDataSize, DataCnt, eOpMode, eSrcReq, eDstReq, eBurstMode, DMAC
DMACH_Setup(DMA_G, 0x0, uRxSrcAddr, 0, rSDMA1_RX_FIFO, 1, WORD, uRxSize, DEMAND, MEM, SDMA1_SECU_RX, BURST8, &oSdma1_RX);
// Tx Destination Setting - using Channel 7 (Tx)
DMACH_Setup(DMA_H, 0x0, rSDMA1_TX_FIFO, 1, uTxDstAddr, 0, WORD, uTxSize, DEMAND, SDMA1_SECU_TX, MEM, BURST8, &oSdma1_TX);
}
//////////
// Function Name : SBLK_StartSDMA
// Function Description : This function start SDMA1
// Input : NONE
// Output : NONE
// Version :
void SBLK_StartSDMA(void)
{
DMACH_Start(&oSdma1_RX);
DMACH_Start(&oSdma1_TX);
}
//////////
// Function Name : SBLK_PutDataToInReg
// Function Description : This function
// Input : uSrcAddr, uSize, eLValid
// Output : NONE
// Version :
void SBLK_PutDataToInReg(u32 uSrcAddr, u32 uSize, LVALID_BYTE eLValid)
{
u32 i, uReg;
u32 *pSrcAddr, *pDstAddr;
pSrcAddr = (u32 *)uSrcAddr;
if (oSblk.m_eSblkType == AES)
{
pDstAddr = (u32 *)rAES_RX_DIN1;
for (i=uSize; i>0; i--)
Outp32(pDstAddr++, *pSrcAddr++);
}
else if (oSblk.m_eSblkType == DES)
{
pDstAddr = (u32 *)rDES_RX_IN0;
for (i=uSize; i>0; i--)
Outp32(pDstAddr++, *pSrcAddr++);
}
else
{
for (i=uSize; i>0; i--)
{
if(i == 1)
{
uReg =
((eLValid == LASTBYTE_1ST)? (0<<6) :
(eLValid == LASTBYTE_2ND)? (1<<6) :
(eLValid == LASTBYTE_3RD)? (2<<6) : (3<<6)) |
HASH_INPUT_FINISHED |
((oSblk.m_eOperMode == HMAC)? (0<<0) :
(oSblk.m_eOperMode == SHA1)? (1<<0) : (2<<0));
Outp32(rHASH_RX_CTRL, uReg); // inform hash of last data input
}
Outp32(rHASH_RX_DAT, *pSrcAddr++);
}
}
}
//////////
// Function Name : SBLK_StartByManual
// Function Description : This function
// Input : NONE
// Output : NONE
// Version :
void SBLK_StartByManual(void)
{
u32 uRead;
if (oSblk.m_eSblkType == AES)
{
uRead = Inp32(rAES_RX_CTRL);
uRead |= (1<<0);
Outp32(rAES_RX_CTRL, uRead);
}
else if (oSblk.m_eSblkType == DES)
{
uRead=Inp32(rDES_RX_CTRL);
uRead |= (1<<0);
Outp32(rDES_RX_CTRL, uRead);
}
else
{
uRead=Inp32(rHASH_RX_CTRL);
uRead |= (1<<3);
Outp32(rHASH_RX_CTRL, uRead);
}
}
//////////
// Function Name : SBLK_GetDataFromOutReg
// Function Description : This function
// Input : uDstAddr, uSize
// Output : NONE
// Version :
void SBLK_GetDataFromOutReg(u32 uDstAddr, u32 uSize)
{
u32 i;
u32 *pSrc, *pDst;
pDst = (u32 *)uDstAddr;
if (oSblk.m_eSblkType == AES)
pSrc = (u32 *)rAES_RX_DOUT1;
else if (oSblk.m_eSblkType == DES)
pSrc = (u32 *)rDES_RX_OUT0;
else if (oSblk.m_eSblkType == HASH)
{
if (oSblk.m_eOperMode == PRNG)
pSrc = (u32 *)rPRNG_TX_OUT1;
else
pSrc = (u32 *)rHASH_OUTPUT_01;
}
for(i=0; i<uSize; i++)
*pDst++ = *pSrc++;
}
void SBLK_GetDataFromOutReg_Test(u32 uDstAddr, u32 uSize)
{
u32 i;
u32 *pSrc, *pDst;
pDst = (u32 *)uDstAddr;
if (oSblk.m_eSblkType == AES)
pSrc = (u32 *)rAES_RX_DOUT1;
else if (oSblk.m_eSblkType == DES)
pSrc = (u32 *)rDES_RX_OUT0;
else if (oSblk.m_eSblkType == HASH)
{
if (oSblk.m_eOperMode == PRNG)
pSrc = (u32 *)rPRNG_TX_OUT1;
else
pSrc = (u32 *)rHASH_TX_OUT1;
}
for(i=0; i<uSize; i++)
*pDst++ = *pSrc++;
}
//////////
// Function Name : SBLK_IsOutputReady
// Function Description : This function
// Input : NONE
// Output : true, false
// Version :
bool SBLK_IsOutputReady(void)
{
u32 uRead, uRet;
if (oSblk.m_eSblkType == AES)
{
uRead=Inp32(rAES_RX_CTRL);
uRet = (uRead>>10)&1;
}
else if (oSblk.m_eSblkType == DES)
{
uRead=Inp32(rDES_RX_CTRL);
uRet = (uRead>>7)&1;
}
else if (oSblk.m_eSblkType == HASH)
{
uRead=Inp32(rHASH_RX_STAT);
if (oSblk.m_eOperMode == PRNG)
uRet = (uRead>>2)&1;
else
uRet = (uRead>>0)&1;
}
if(uRet)
return true;
else
return false;
}
void SBLK_DispFifoRxCtrl(u32 uFRx_Ctrl)
{
//FIFO-RX
Disp("++++++++START FIFO-RX Ctrl Value++++++++++++++++++++++++++++++++++++++++++++++++++\n\n");
Disp("FRx_Start = %d => It should be zero when FIFO starts Transfer.\n",(uFRx_Ctrl>>0) & 0x1);
Disp("FRx_ERROR_En = %d => Enables ERROR response via HRESP port when host tries to access FIFO-RX.\n",(uFRx_Ctrl>>1) & 0x1);
Disp(" And Access is not enabled by FRx_Ctrl[4] 0r [5].\n");
Disp("FRx_Reset = %d => Enables ERROR response via HRESP port when host tries to access FIFO-RX.\n",(uFRx_Ctrl>>2) & 0x1);
Disp("FRx_Sync_Tx = %d => Waits for FIFO_TX Done.\n",(uFRx_Ctrl>>3) & 0x1);
Disp("FRx_Host_Wr_En = %d => Enables Host write to FRx_WrBuf.\n",(uFRx_Ctrl>>4) & 0x1);
Disp("FRx_Host_Rd_En = %d => Enables Host read from FRx_Ctrl[31:16] and FRx_MLenCnt.\n",(uFRx_Ctrl>>5) & 0x1);
Disp("FRx_Dest_Module = %d => Destination Module Selection 0:AES, 1:DES, 2:SHA-1/PRNG,3:NA.\n",(uFRx_Ctrl>>6) & 0x3);
Disp("FRx_Wd2Read = %d => Number of words that can be read from FIFO Memory(FRx_WrBuf\n",(uFRx_Ctrl>>8) & 0xff);
Disp("FRx_Wd2Write = %d => Number of words that can be written to FIFO Memory(FRx_WrBuf\n",(uFRx_Ctrl>>16) & 0xff);
Disp("FRx_Running = %d => Set to 1 if FIFO-RX is transfering data to the destination or waiting for destination input beffer ready\n",(uFRx_Ctrl>>24) & 0x1);
Disp(" Set to 1 when FRx_Start bit resets to 0. ReadONly\n");
Disp("FRx_Done = %d => Set to 1 if FIFO-RX finished transfering data to the destination\n",(uFRx_Ctrl>>25) & 0x1);
Disp("FRx_Empty = %d => Set to 1 if FIFO Buffer(FRx_WrBuf) is Empty\n",(uFRx_Ctrl>>26) & 0x1);
Disp("FRx_Full = %d => Set to 1 if FIFO Buffer(FRx_WrBuf) is Full\n",(uFRx_Ctrl>>27) & 0x1);
Disp("++++++++END FIFO-RX Ctrl Value++++++++++++++++++++++++++++++++++++++++++++++++++\n\n");
}
void SBLK_DispFifoTxCtrl(u32 uFTx_Ctrl)
{
//FIFO-TX
Disp("++++++++START FIFO-TX Ctrl Value++++++++++++++++++++++++++++++++++++++++++++++++++\n\n");
Disp("FTx_Start = %d => It should be zero when FIFO starts Transfer.\n",(uFTx_Ctrl>>0) & 0x1);
Disp("FTx_ERROR_En = %d => Enables ERROR response via HRESP port when host tries to access FIFO-TX.\n",(uFTx_Ctrl>>1) & 0x1);
Disp(" And Access is not enabled by FTx_Ctrl[4] 0r [5].\n");
Disp("FTx_Reset = %d => Enables ERROR response via HRESP port when host tries to access FIFO-TX.\n",(uFTx_Ctrl>>2) & 0x1);
Disp("FTx_Reserved = %d => Reserved.\n",(uFTx_Ctrl>>3) & 0x1);
Disp("FTx_Host_Wr_En = %d => Enables Host write to FRx_WrBuf.\n",(uFTx_Ctrl>>4) & 0x1);
Disp("FTx_Host_Rd_En = %d => Enables Host read from FTx_Ctrl[31:16] and FTx_MLenCnt.\n",(uFTx_Ctrl>>5) & 0x1);
Disp("FTx_Src_Module = %d => Destination Module Selection 0:AES, 1:DES, 2:SHA-1/PRNG,3:NA.\n",(uFTx_Ctrl>>6) & 0x3);
Disp("FTx_Wd2Write = %d => Number of words that can be read from FIFO Memory(FTx_WrBuf\n",(uFTx_Ctrl>>8) & 0xff);
Disp("FTx_Wd2Read = %d => Number of words that can be written to FIFO Memory(FTx_WrBuf\n",(uFTx_Ctrl>>16) & 0xff);
Disp("FTx_Running = %d => Set to 1 if FIFO-TX is transfering data to the destination or waiting for destination input beffer ready\n",(uFTx_Ctrl>>24) & 0x1);
Disp(" Set to 1 when FRx_Start bit resets to 0. ReadONly\n");
Disp("FTx_Done = %d => Set to 1 if FIFO-TX finished transfering data to the destination\n",(uFTx_Ctrl>>25) & 0x1);
Disp("FTx_Empty = %d => Set to 1 if FIFO Buffer(FTx_WrBuf) is Empty\n",(uFTx_Ctrl>>26) & 0x1);
Disp("FTx_Full = %d => Set to 1 if FIFO Buffer(FTx_WrBuf) is Full\n",(uFTx_Ctrl>>27) & 0x1);
Disp("++++++++END FIFO-TX Ctrl Value++++++++++++++++++++++++++++++++++++++++++++++++++\n\n");
}
void SBLK_Init_Test(SBLK_TYPE eSblkType, OPER_MODE eOperMode, DIR_SEL eDirSel)
{
u32 uReg;
u32 *pSrc;
int i;
int uSel, uSel1;
oSblk.m_eSblkType = eSblkType;
oSblk.m_eOperMode = eOperMode;
SBLK_Reset();
if (oSblk.m_eSblkType == AES)
{
printf(" Choose AES Key Select : 0 : 128bit, 1:192bit, 2:256bits, 3: Counter \n");
uSel = GetIntNum();
switch(uSel)
{
case 0:
Copy((u32)uAesKey, rAES_RX_KEY1, 4); // install aes key
Copy((u32)uAesIV, rAES_RX_IV1, 4); // install aes iv
Copy((u32)uAesInitCounter, rAES_RX_CTR1, 4); // install ctr data
uReg = (eDirSel == ENC)? (0<<3) : (1<<3);
if (oSblk.m_eOperMode == ECB)
uReg |= (1<<4);
else if (oSblk.m_eOperMode == CBC)
uReg |= (2<<4);
else if (oSblk.m_eOperMode == CTR)
uReg |= (3<<4);
else
Assert(0);
Outp32(rAES_RX_CTRL, uReg);
break;
case 1:
Copy((u32)uAesKey, rAES_RX_KEY1, 4); // install aes key
Copy((u32)uAesKey, rAES_RX_KEY5, 2); // install aes key
Copy((u32)uAesIV, rAES_RX_IV1, 4); // install aes iv
Copy((u32)uAesInitCounter, rAES_RX_CTR1, 4); // install ctr data
uReg = (eDirSel == ENC)? (0<<3) : (1<<3);
uReg |= (1<<1);
if (oSblk.m_eOperMode == ECB)
uReg |= (1<<4);
else if (oSblk.m_eOperMode == CBC)
uReg |= (2<<4);
else if (oSblk.m_eOperMode == CTR)
uReg |= (3<<4);
else
Assert(0);
Outp32(rAES_RX_CTRL, uReg);
break;
case 2:
Copy((u32)uAesKey, rAES_RX_KEY1, 4); // install aes key
Copy((u32)uAesKey, rAES_RX_KEY5, 4); // install aes key
Copy((u32)uAesIV, rAES_RX_IV1, 4); // install aes iv
Copy((u32)uAesInitCounter, rAES_RX_CTR1, 4); // install ctr data
uReg = (eDirSel == ENC)? (0<<3) : (1<<3);
uReg |= (2<<1);
if (oSblk.m_eOperMode == ECB)
uReg |= (1<<4);
else if (oSblk.m_eOperMode == CBC)
uReg |= (2<<4);
else if (oSblk.m_eOperMode == CTR)
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