sysc.c

s3c6400 ADS下官方测试程序

	uOffset = (eBusId&0xF00)>>8;
	uPType = (eBusId&0x0F0)>>4;
	uForder = eBusId&0x00F;

	if(uOffset <= 3)
	{
		uOffset1 = uOffset;
		uRegValue = Inp32(rAHB_CON0);
		uRegValue = (uRegValue & ~(0xFF<<(uOffset1*7))) | ((uPType<<(uOffset1*7 + 4))|(uForder<<(uOffset1*7)));
		Outp32(rAHB_CON0, uRegValue);
	}
	else if(uOffset >= 4 && uOffset <= 7)
	{
		uOffset1 = uOffset - 4;
		uRegValue = Inp32(rAHB_CON1);
		uRegValue = (uRegValue & ~(0xFF<<(uOffset1*7))) | ((uPType<<(uOffset1*7 + 4))|(uForder<<(uOffset1*7)));
		Outp32(rAHB_CON1, uRegValue);
	}
	else if(uOffset >= 8 && uOffset <= 9)
	{
		uOffset1 = uOffset - 8;
		uRegValue = Inp32(rAHB_CON2);
		uRegValue = (uRegValue & ~(0xFF<<(uOffset1*7))) | ((uPType<<(uOffset1*7 + 4))|(uForder<<(uOffset1*7)));
		Outp32(rAHB_CON2, uRegValue);
	}

}



//////////
// Function Name : SYSC_CtrlBUSLock
// Function Description : This function control HLOCK for each bus
//				 
// Input : 		  
// Output : NONE
// Version : 


//  TBD



//////////
// Function Name : SYSC_SeletDMA
// Function Description : This function select between SDMA and General DMA
//				 
// Input : 		  	SEL_eSDMA : 
//					uSEL     :  #define		SEL_SDMA		(0)
//							 #define		SEL_GDMA		(1)
//							  
// Output : NONE
// Version : 
void SYSC_SelectDMA( DMASELECT_eID eSEL_DMA, u32 uSEL)
{
	u32 uRegValue;
	u32 uOffset;

	uOffset = eSEL_DMA;	
	uRegValue =Inp32(rSDMA_SEL);
	
	uRegValue = (uRegValue & ~(0x1<<uOffset)) | (uSEL<<uOffset);
	Outp32(rSDMA_SEL, uRegValue);

}



//////////
// Function Name : SYSC_CtrlEBIPrio
// Function Description : This function control EBI Priority
//				 
// Input : 		  EBIPrio_eID
// Output : NONE
// Version : 
void SYSC_CtrlEBIPrio( EBIPrio_eID  eEBIId)
{
	u32 uPType, uForder;
	u32 uRegValue;

	uPType = (eEBIId&0xF0)>>4;
	uForder = eEBIId&0x0F;

	uRegValue = Inp32(rMEM_SYS_CFG);
	uRegValue = (uRegValue & ~(0xF<<8)) | ((uPType<<11)|(uForder<<8));
	Outp32(rMEM_SYS_CFG, uRegValue);

}

//////////
// Function Name : SYSC_CtrlCSMEM0
// Function Description : This function control static memory chip selection muxing of MEM0
//				 
// Input : 		  			eM0CSn2 : eCS_SROMC, eCS_ONDC, eCS_NFC
//							eM0CSn3 : eCS_SROMC, eCS_ONDC, eCS_NFC
//							eM0CSn4 : eCS_SROMC, eCS_CFC
//							eM0CSn5 : eCS_SROMC, eCS_CFC
// Output : NONE
// Version : 
void SYSC_CtrlCSMEM0( SelCS_eMEM0  eM0CSn2, SelCS_eMEM0 eM0CSn3, SelCS_eMEM0 eM0CSn4, SelCS_eMEM0 eM0CSn5 )
{
	u32 uRegValue;

	uRegValue = Inp32(rMEM_SYS_CFG);
	uRegValue = (uRegValue & ~(0x3F<<0)) | ((eM0CSn5<<5)|(eM0CSn4<<4)|(eM0CSn3<<2)|(eM0CSn2<<0));
	Outp32(rMEM_SYS_CFG, uRegValue);

}


//////////
// Function Name : SYSC_SetQos
// Function Description : This function set QOS_OV_ID
//				 
// Input : 		  
// Output : NONE
// Version : 


//  TBD


//////////
// Function Name : SYSC_RdMEMCFG
// Function Description : This function read MEM_CFC_STAT Register
//				 
// Input :   NONE	  			
// Output : NONE
// Version : 
void SYSC_RdMEMCFGSTAT( void )
{
	u32 uRegValue;
	u32 uTemp;

	uRegValue = Inp32(rMEM_CFG_STAT);

	// EBI Priority Scheme
	uTemp = ( uRegValue >>15 ) & 0x1;
	printf(" Current EBI Priority Scheme 	(0: Fixed, 1: Circular) :    %d \n",  uTemp);
	uTemp = (uRegValue >> 12) & 0x7 ;
	printf(" Current EBI Fixed Priority setting					 :    %d \n",  uTemp);

	// CF I/F
	uTemp = ( uRegValue >>10 ) & 0x1;
	printf(" Current CF I/F Setting  (0: EBI, 1: Independet)	 :    %d \n",  uTemp);

	// NAND Type Setting
	uTemp = ( uRegValue >>9 ) & 0x1;
	printf(" Current NAND Type (0:OneNAND, 1: NAND)		 :    %d \n",  uTemp);
	uTemp = ( uRegValue >>3 ) & 0x1;
	printf(" Current NAND Init Setting  (0: Normal NAND, 1: Advanced NAND)	 :    %d \n",  uTemp);
	uTemp = ( uRegValue >>2 ) & 0x1;
	printf(" Show address cycle init. setting of NAND  	 :    %d \n",  uTemp);
	uTemp = ( uRegValue >>0 ) & 0x1;
	printf(" Show NAND Page Size	 :    %d \n",  uTemp);

	uTemp = ( uRegValue >>8 ) & 0x1;
	printf(" Current CS0 Bus Width  (0: 8-bit, 1: 16-bit)		 :    %d \n",  uTemp);
	uTemp = ( uRegValue >>1 ) & 0x1;
	printf(" Show CS0 Bus width (init. Setting)  (0:8bit, 1: 16bit)	 :    %d \n",  uTemp);

	uTemp = ( uRegValue >>7 ) & 0x1;
	printf(" NAND Booting   (0: not Used, 1: used)	 		:    %d \n",  uTemp);

	uTemp = ( uRegValue >>5 ) & 0x3;
	printf(" Current Booting Type  (0: NFCON, 1: SROMC, 2: ONDC,  3: Internal ROM)	 :    %d \n",  uTemp);

	uTemp = ( uRegValue >>4 ) & 0x1;
	printf(" Current ADDR Expand  (0: Used MEM1 Data, 1:Used MEM0 Addr)	 :    %d \n",  uTemp);


}

//////////
// Function Name : SYSC_SetCFGWFI
// Function Description : This function configure ARM1176 STANBYWFI ( CFG_STANDBY (in PWR_CFG Register))
//				  ( CFG_STANDBYWFI & OSC Control in Power Mode )
// Input : 		  	eWFIMode : eIGNORE, eIDLE, eSTOP, eSLEEP
//					uOSCCLK     :  #define		Disable_CLK		(0)
//								 #define		Enable_CLK		(1)
//							  
// Output : NONE
// Version : 
void SYSC_SetCFGWFI( CFG_eWFI eWFIMode, u32 uOSCCLK)
{
	u32 uRegValue, uRegValue1;

	uRegValue =Inp32(rPWR_CFG);

	switch(eWFIMode)
	{
		case eIGNORE: 
			uRegValue = (uRegValue & ~(0x61<<0)) | ((eWFIMode<<5)|(1<<0));		// CFG_STANDBY= ignore,  OSC_27 = Enable
			Outp32(rPWR_CFG, uRegValue);  break;
		case eIDLE: 
			uRegValue = (uRegValue & ~(0x61<<0)) | ((eWFIMode<<5)|(uOSCCLK<<0));		
			Outp32(rPWR_CFG, uRegValue);  break;
		case eSTOP: 
			uRegValue = (uRegValue & ~(0x61<<0)) | ((eWFIMode<<5)|(uOSCCLK<<0));
			uRegValue1=Inp32(rSTOP_CFG);
			uRegValue1 = (uRegValue1 & ~(0x3<<0)) | ((uOSCCLK<<1)|(uOSCCLK<<0));
			//uRegValue1 = (uRegValue1 & ~(0x3<<0)) | ((uOSCCLK<<1)|(1<<0));
			Outp32(rPWR_CFG, uRegValue); 
			Outp32(rSTOP_CFG, uRegValue1); 
			break;
		case eSLEEP: 
			uRegValue = (uRegValue & ~(0x61<<0)) | ((eWFIMode<<5)|(uOSCCLK<<0));
			uRegValue1=Inp32(rSLEEP_CFG);
			uRegValue1 = (uRegValue1 & ~(0x61<<0)) | ((uOSCCLK<<0));
			Outp32(rPWR_CFG, uRegValue); 
			Outp32(rSLEEP_CFG, uRegValue1); 
			break;
								
	}

}

//////////
// Function Name : SYSC_SetBATF
// Function Description : This function configure BATFLT ( (in PWR_CFG Register))
//				  
// Input : 		  	eBATFLT : eFLT_IGNORE, eFLT_INT, eFLT_SLEEP
//					uINTSRC     :  (0) Wake-up Source in ESLEEP :  nWRESET
//								(1) Wake-up Source in ESLEEP :  SLEEP Wake-up Source
//		
//							  
// Output : NONE
// Version : 
void SYSC_SetBATF( BATFLT_eMODE eBATFLT, u32 uINTSRC)
{
	u32 uRegValue;

	uRegValue =Inp32(rPWR_CFG);

	switch(eBATFLT)
	{
		case eFLT_IGNORE: 
			uRegValue = (uRegValue & ~(0x1F<<0)) | ((eBATFLT<<3)|(1<<0));		
			Outp32(rPWR_CFG, uRegValue);  break;
		case eFLT_INT: 
			uRegValue = (uRegValue & ~(0x1F<<0)) | ((eBATFLT<<3)|(1<<0));		
			Outp32(rPWR_CFG, uRegValue);  break;
		case eFLT_SLEEP: 
			uRegValue = (uRegValue & ~(0x1F<<0)) | ((eBATFLT<<3)|(uINTSRC<<2)|(1<<0));
			Outp32(rPWR_CFG, uRegValue); 
			break;					
	}

}

//////////
// Function Name : SYSC_SetSTOPCFG
// Function Description : This function configure Power Control of the internal block in the Stop Mode 
//				  
// Input : 		  	uMEM_ARM :  Power Control of the Memory Block in ARM Module (0: OFF, 1:ON)
//					uMEM_TOP :  Power Control of the Memory Block in Top Module (0: OFF, 1:ON)
//					uLogic_ARM :  Power Control of the Logic Block in ARM Module (0: OFF, 1:ON)
//					uLogic_ARM :  Power Control of the Logic Block in Top Module (0: OFF, 1:ON)		  
// Output : NONE
// Version : 
void SYSC_SetSTOPCFG( u32 uMEM_ARM, u32 uMEM_Top, u32 uLogic_ARM, u32 uLogic_Top)
{
	u32 uRegValue;

	uRegValue =Inp32(rSTOP_CFG);
	uRegValue = (uRegValue & ~(0x3FFFFF<<8)) | ((uMEM_ARM<<29)|(uMEM_Top<<20)|(uLogic_ARM<<17)|(uLogic_Top<<8));
	Outp32(rSTOP_CFG, uRegValue); 
}


//////////
// Function Name : SYSC_SetWakeMASK
// Function Description : This function control Wake-up source Mask  
//				  
// Input : 		  	WKUPMSK_eID : Wake-up Source ID
//					uMaskCtrl     :  (0) Mask disable , Wake-up source Enable
//								 (1) Mask Enable,  Wake-up source disable
//		
//							  
// Output : NONE
// Version : 
void SYSC_SetWakeMASK( WKUPMSK_eID eWKUPSRC, u32 uMaskCtrl)
{
	u32 uRegValue;
	u32 uRegOffset, uMaskID;

	uRegOffset = (eWKUPSRC&0xF00)>>8;
	uMaskID = eWKUPSRC&0x0FF;

	if(uRegOffset == 0)
	{
		uRegValue =Inp32(rPWR_CFG);
		uRegValue = (uRegValue & ~(0x1<<(uMaskID+7))) | (uMaskCtrl<<(uMaskID+7));	
		Outp32(rPWR_CFG, uRegValue);
	}
	else if(uRegOffset == 1)
	{
		uRegValue = Inp32(rEINT_MASK);
		uRegValue = (uRegValue & ~(0x1<<(uMaskID))) | (uMaskCtrl<<(uMaskID));
		Outp32(rEINT_MASK, uRegValue);
	}
	
}


//////////
// Function Name : SYSC_CtrlNORCFG
// Function Description : This function control Block Power off of the internal logic during normal operation 
//				  
// Input : 		  	eCFGId : Internal block  Domain Id
//					uPwrCtrl     :   (0) LP mode,  Block Power Off
//								 (1) Active mode, Block Power ON
//		
//							  
// Output : NONE
// Version : 
void SYSC_CtrlNORCFG( NORGFC_eID eCFGId, u32 uPwrCtrl)
{
	u32 uRegValue, uTemp;

	uRegValue =Inp32(rNORMAL_CFG);
	uTemp = eCFGId;

       uRegValue = (uRegValue & ~(1<<uTemp)) | (uPwrCtrl <<uTemp);
	Outp32(rNORMAL_CFG, uRegValue);
		
}

//////////
// Function Name : SYSC_ChangeMode
// Function Description : This function change Operating Mode
//				  
// Input : 		  	
//					eOPMode     :   eASYNC_MODE(0) Asynchronous mode
//								  eSYNC_MODE (1) Synchronous mode
//		
//							  
// Output : NONE
// Version : 
void SYSC_ChangeMode(SYSC_eOPMode eOPMode)
{
	u32 uRegValue,  uCurrMode, uDIV0, uDIV0_org, uSRC, uSRC_org;
	u32 uHCLKx2_Ratio;

	uRegValue =Inp32(rOTHERS);
	uCurrMode = (uRegValue >> 8 ) & 0xF ;
	uDIV0_org = Inp32(rCLK_DIV0);
	uSRC_org = Inp32(rCLK_SRC);
	uHCLKx2_Ratio=(uDIV0_org>>9)&0x7;

	
	if((eOPMode == 0)&&(uCurrMode == 0xF))				// Current = SyncMode, Next = AsyncMode	
	{
		// For FirmWare Test => APLL Out = MPLL*2
		if(uHCLKx2_Ratio == 0)
			{
				uDIV0_org = uDIV0_org;
			}
		else 
			{
				uDIV0_org = (uDIV0_org & ~(0x7<<9)) | (0 <<9);
			}
		
		uSRC = (uSRC_org & ~(0x3<<0)) | (0 <<0);				// A&MPLL Change to Clock Source
		uDIV0 = (uDIV0_org & ~(0xFFFF<<0)) | (0x1100 <<0);	// Clock Divider 1:1 ??

		Outp32(rCLK_SRC, uSRC);
		Outp32(rCLK_DIV0, uDIV0);
		
		uRegValue = (uRegValue & ~(0x3<<6)) | (1 <<6);		// SYNCMODE(SYNCREQ) = ASYNC, VICEN= Async, MUXSEL=Sync
		Outp32(rOTHERS, uRegValue);

		while(((Inp32(rOTHERS)>>8)&0x7));				// Wait SYNCMODEACK = 0x0

		uRegValue = Inp32(rOTHERS);
		uRegValue = (uRegValue&~(0x1<<6)) | (0<<6);		// Change SYNCMUX to AsyncMode
		Outp32(rOTHERS, uRegValue);

		Outp32(rCLK_DIV0, uDIV0_org);
		Outp32(rCLK_SRC, uSRC_org);

		
	}
	else if ((eOPMode == 1)&&(uCurrMode == 0x0))			// Current = AsyncMode, Next = SyncMode	
	{

		uSRC = (uSRC_org & ~(0x3<<0)) | (0 <<0);				// A&MPLL Change to Clock Source
		uDIV0 = (uDIV0_org & ~(0xFFFF<<0)) | (0x1100 <<0);	      // Clock Divider 1:1 ??

		if(uHCLKx2_Ratio == 0)
			{
				uDIV0_org = (uDIV0_org & ~(0x7<<9)) | (1 <<9);
			}
		else 
			{
				uDIV0_org = uDIV0_org;
				
			}

		Outp32(rCLK_SRC, uSRC);
		Outp32(rCLK_DIV0, uDIV0);
	
		uRegValue = (uRegValue & ~(0x1<<6)) | (1 <<6);		// Change SYNCMUX to SyncMode
		Outp32(rOTHERS, uRegValue);

		__asm {

			nop;
			nop;
			nop;
			nop;
			nop;
			
			}											// Wait for a while (TBD)

		uRegValue = (uRegValue & ~(0x1<<7)) | (1 <<7);		// SYNCMODE = SYNC, VICEN=SYNC, MUXSEL=SYNC
		Outp32(rOTHERS, uRegValue);
		
		while(((Inp32(rOTHERS)>>8)&0x7) == 0xF);			// Wait SYNCMODEACK = 0xF

		
		Outp32(rCLK_DIV0, uDIV0_org);
	
		Outp32(rCLK_SRC, uSRC_org);
	
	}

	Delay(10);
		
}

//////////
// Function Name : SYSC_ClrBATFINT
// Function Description : This function clear int pending bit about nBATF Int.
//				  
// Input : 		  	
//							  
// Output : NONE
// Version : 
void SYSC_ClrBATFINT(void)
{
	u32 uRegValue;