clock_test.c

s3c6400 ADS下官方测试程序

void Return_Condition(void)
{

	u32 uTemp, uTemp1,uRegValue_APLL, uRegValue_DIV0, uRegValue_SRC;
	
	g_iPvalue = 3;
	g_iMvalue = 400;
	g_iSvalue = 2;
	
	g_iARMCLK_DIVN_R = 0;
	g_iHCLKx2_DIVN_R   = 1;
	g_iPCLK_DIVN_R   = 3;


	//SYSC_SetDIV0(g_iARMCLK_DIVN_R, 1, 1, g_iHCLKx2_DIVN_R,  g_iPCLK_DIVN_R, 1, 1,0, 1, 0);
	//SYSC_SetPLL(eAPLL, g_iMvalue, g_iPvalue, g_iSvalue, 0 );	

	// EVT0 - 07.02.28
	uRegValue_APLL =  (u32)(((u32)(0x1<<31))|(g_iMvalue<<16)|(g_iPvalue<<8)|(g_iSvalue<<0));
	
	// Clock Divider Change 1:2:2
	uRegValue_DIV0 = Inp32SYSC(0x20);
	uTemp = (uRegValue_DIV0&~(0xFFFF))|(1<<12)|((0<<9)|(1<<8)|(1<<4)|(0<<0));		// ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
	uRegValue_DIV0 = (uRegValue_DIV0&~(0xFFFF))|(g_iPCLK_DIVN_R<<12)|((g_iHCLKx2_DIVN_R<<9)|(1<<8)|(1<<4)|(g_iARMCLK_DIVN_R<<0));

	uRegValue_SRC = Inp32SYSC(0x1C);
	uTemp1 = (uRegValue_SRC&~(0x7))|0x0;

	Outp32SYSC(0x1c, uTemp1);	// Clock Source Change
	Outp32SYSC(0x20, uTemp);	// Change Clock Divider


	//PLL Change
	Outp32SYSC(0xc, uRegValue_APLL);

	while(((Inp32SYSC(0xc)>>30)&0x1)==0);

	// Change Divider Value
	Outp32SYSC(0x20, uRegValue_DIV0);
	// Change Clock SRC
	Outp32SYSC(0x1c, uRegValue_SRC);
	Delay(100);
	
	SYSC_GetClkInform(); 
	UART_InitDebugCh(0, 115200);
	Delay(100);
	printf(" Re Back_UP\n");
	
	printf("============================ \n");
	printf("Current Clock Information \n");
	printf("ARMCLK: %.2fMHz  HCLKx2: %.2fMHz  HCLK: %.2fMHz  PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
	printf("============================ \n");
	
	
	for ( g_iRoop1 = 0 ; g_iRoop1 < 32 ; g_iRoop1++ )
	{
		iCompare_R[g_iRoop1] = 0x7ff;
	}
	for ( g_iRoop4 = 0 ; g_iRoop4 < 18 ; g_iRoop4++ )
	{
		iCompare_PMS[g_iRoop4] = 0x3ffff;
	}
	
	g_iAPLL   = 400;
	g_iAPLL_0 = 400;
	g_iCompare_0 = 0;
	g_iCompare_1 = 0;
	g_iSum = 0;
	g_iRoop = 0;
	g_iRoop1 = 0;
	g_iRoop2 = 0;
	g_iRoop3 = 0;
	g_iRoop4 = 0;
	g_iRoop5 = 0;
	g_iRoop6 = 0;
	g_iRoop7 = 0;
		
	Delay(100);

}

void Select_Random_DIVN(void)
{
	//u32 iARMCLK=0,iHCLKx2=0, iHCLK=0, iPCLK=0;
	float fARMCLK=0 ,fHCLKx2=0, fHCLK=0, fPCLK=0;
	u32 u_iHCLK_DIVN_R=1;
	
	g_iAPLL_0 = g_iAPLL;
	
	while(1)
	{

		//for test
		DisplayLED(g_iRoop/1000);
		if(UART_GetKey()!=0x0) 
			break;
		if(g_iRoop5==10) 
			break;
		/*
		if ((g_iRoop%10000)==0)
		{	
			SYSC_GetClkInform();		
			UART_InitDebugCh(0, 115200);
			Delay(1000);
			printf("\n%d \n", g_iRoop);
		}
		*/

	
		//g_iARMCLK_DIVN_R  = ( rand()%16 );
		g_iARMCLK_DIVN_R = 0;					// EVT0, Sync Mode...
		g_iHCLKx2_DIVN_R   = ( (rand()%7 )+1 );	// Sync. Min. 1
		g_iPCLK_DIVN_R    = (( rand()%15 )+1);		// PCLK  =< HCLK
		
		//fARMCLK = (float)(g_iAPLL   /  (g_iARMCLK_DIVN_R+1));
		// EVT0 - Sync. Mode
		fARMCLK = (float)(g_iAPLL   /  (0+1));
		fHCLKx2   = (float)(g_iAPLL /  (g_iHCLKx2_DIVN_R+1));
		fHCLK   =(float)(fHCLKx2   / (u_iHCLK_DIVN_R +1));
		fPCLK   = (float)(fHCLKx2  / (g_iPCLK_DIVN_R+1));

		if(((g_iPCLK_DIVN_R%2)==1) &&( fARMCLK<=540 & fHCLK <= 133 & fPCLK <= 66.5 )	)
		//if ( fARMCLK<=540 & fHCLK <= 133 & fPCLK <= 66.5 )		
		{
		 	g_iRoop ++;
			break;  	
		}
	}

	//printf("Random Choice= HCLKx2 Ratio = %d, PCLK Ratio = %d \n", g_iHCLKx2_DIVN_R, g_iPCLK_DIVN_R);
}

void Compare_Logic_DIVN(void)
{
	if ( g_iRoop == 1 )
	{
		g_iCompare_0 = iDivn[g_iARMCLK_DIVN_R][g_iHCLKx2_DIVN_R][g_iPCLK_DIVN_R];
	}
	else 
	{
		g_iCompare_1 = iDivn[g_iARMCLK_DIVN_R][g_iHCLKx2_DIVN_R][g_iPCLK_DIVN_R] ;
	}

	if ( g_iRoop >= 2 )
	{	
		//org
		iCompare_R[g_iCompare_0] = iCompare_R[g_iCompare_0] & (~(1<<g_iCompare_1)) ; 
		//iCompare_R[g_iCompare_0] = iCompare_R[g_iCompare_0] & (~(1<<(g_iRoop%12))) ; 
		g_iSum = 0;
		for ( g_iRoop1 = 0 ; g_iRoop1 < 32 ;g_iRoop1++ )
		{
			g_iSum = g_iSum + iCompare_R[g_iRoop1];
		}
		if (g_iSum == 0 )
		{
				
			printf( "\n------------------> Test End!!! %d Rotation \n " , g_iRoop );
			g_iRoop5++;
			for ( g_iRoop1 = 0 ; g_iRoop1 < 32 ; g_iRoop1++ )
			{
				iCompare_R[g_iRoop1] = 0x7ff;
			}
			printf ( "------------------> %d th Test OK \n", g_iRoop5);
			if ( g_iRoop5 == 10 )
			{
				//UART_Getc();	
				printf("Change and Retest another Chip\n");
				//g_iRoop5 = 0;
				
			}
		}
		g_iCompare_0 = g_iCompare_1;
	}
	
}

/*
void Data_Compare_Init(void)
{	// ARM_Ratio, HCLKx2 Ratio,  PCLK Ratio
	iDivn[0][0][3] = 0;
	iDivn[1][1][4] = 1;
	iDivn[2][1][5] = 2;
	iDivn[3][2][6] = 3;
	iDivn[4][2][7] = 4;
	iDivn[5][3][8] = 5;
	iDivn[6][3][9] = 6;
	iDivn[7][4][10] = 7;
	iDivn[8][4][11] = 8;
	iDivn[9][5][12] = 9;
	iDivn[10][5][13] = 10;
	iDivn[11][6][14] = 11;
	iDivn[12][6][15] = 12;
	iDivn[13][7][3] = 13;
	iDivn[14][7][4] = 14;
	iDivn[15][8][5] = 15;
	iDivn[0][8][6] = 16;
	iDivn[1][9][7] = 17;
	iDivn[2][9][8] = 18;
	iDivn[3][10][9] = 19;
	iDivn[4][10][10] = 20;
	iDivn[5][11][11] = 21;
	iDivn[6][11][12] = 22;
	iDivn[7][12][13] = 23;
	iDivn[8][12][14] = 24;
	iDivn[9][13][15] = 25;
	iDivn[10][13][15] = 26;
	iDivn[11][14][15] = 27;
	iDivn[12][14][15] = 28;
	iDivn[13][15][15] = 29;
	iDivn[14][0][15] = 30;
	iDivn[15][15][15] = 31;
	
}
*/
// Sync Mode = HCLKx2 (1~15),  PCLK = Odd Number, 
void Data_Compare_Init(void)
{	// ARM_Ratio, HCLKx2 Ratio,  PCLK Ratio
	iDivn[0][1][3] = 0;
	iDivn[0][1][5] = 1;
	iDivn[0][1][7] = 2;
	iDivn[0][1][9] = 3;
	iDivn[0][1][11] = 4;
	iDivn[0][1][13] = 5;
	iDivn[0][1][15] = 6;
	iDivn[0][2][3] = 7;
	iDivn[0][2][5] = 8;
	iDivn[0][2][7] = 9;
	iDivn[0][2][9] = 10;
	iDivn[0][2][11] = 11;
	iDivn[0][2][13] = 12;
	iDivn[0][2][15] = 13;
	iDivn[0][3][1] = 14;
	iDivn[0][3][3] = 15;
	iDivn[0][3][5] = 16;
	iDivn[0][3][7] = 17;
	iDivn[0][4][9] = 18;
	iDivn[0][4][11] = 19;
	iDivn[0][4][13] = 20;
	iDivn[0][4][15] = 21;
	iDivn[0][5][1] = 22;
	iDivn[0][5][3] = 23;
	iDivn[0][5][5] = 24;
	iDivn[0][6][7] = 25;
	iDivn[0][6][9] = 26;
	iDivn[0][6][11] = 27;
	iDivn[0][7][13] = 28;
	iDivn[0][7][15] = 29;
	iDivn[0][7][1] = 30;
	iDivn[0][7][3] = 31;
	
}

//////////
// File Name : Test_PMS_Value_Change
// File Description : This function is for PLL Test.  The PMS Value of the APLL is changed randomly
//				 
// Input : 			
//
//						
// Output : NONE
// Version : 
void Test_PMS_Value_Change(void)
{
	u32 uSelPLL;
	
	Insert_Seed(); 

	printf("Choose  PLL :  0 : APLL,  1: MPLL \n");

	uSelPLL = GetIntNum();

	printf("\n");
	printf("If You Start Test, Press Any Key!!!\n");
	printf("Press 'x' : Stop Test\n\n");
	UART_Getc();

	// CLK Output PAD Enable
	
	SYSC_SetLockTime(eAPLL, 100);
	SYSC_SetLockTime(eMPLL, 100);


	switch(uSelPLL)
	{
		case 0:
				SYSC_CtrlCLKOUT( eCLKOUT_APLLOUT, 9); // for clock test, jangwj
				while(!UART_GetKey())
			   	{
					Select_PMS_Random();
					Apply_PMS();
					Compare_PMS_Logic();
			   	}
		 		break;
		case 1:
				SYSC_CtrlCLKOUT( eCLKOUT_HCLK, 4); // for clock test, jangwj
				while(!UART_GetKey())
			   	{
					Select_PMS_Random_M();
					Apply_PMS_M();
					Compare_PMS_Logic();
			   	}
				   		
				break;
	}

		Return_Condition();	
	
}


void Test_PMS_Value_Change_MPLL(void)
{
	Insert_Seed(); 
		
	printf("\n");
	printf("If You Start Test, Press Any Key!!!\n");
	printf("Press 'x' : Stop Test\n\n");
	UART_Getc();

	// CLK Output PAD Enable
	SYSC_CtrlCLKOUT( eCLKOUT_HCLK, 4); // for clock test, jangwj

	SYSC_SetLockTime(eAPLL, 100);
	SYSC_SetLockTime(eMPLL, 100);
	
	while(!UART_GetKey())
   	{
		Select_PMS_Random_M();
		Apply_PMS_M();
		Compare_PMS_Logic();
   	}
   	Return_Condition();
}




//////////
// File Name : Test_Random_DIVN
// File Description : This function is  sub test function for "Test_DIVN_Value_Change"
//				 
// Input : 			
//
//						
// Output : NONE
// Version : 
void Test_Random_DIVN(void)
{

		g_iAPLL = 532;  // for test

		Select_Random_DIVN();
		
		//SYSC_SetDIV0(g_iARMCLK_DIVN_R, 1, 1, g_iHCLKx2_DIVN_R,  g_iPCLK_DIVN_R, 1, 1,0, 1, 0);
		//Sync Mode
		SYSC_SetDIV0(0, 1, 1, g_iHCLKx2_DIVN_R,  g_iPCLK_DIVN_R, 1, 1,0, 1, 0);
		SYSC_GetClkInform(); 
		UART_InitDebugCh(0, 115200);
		Delay(100);
/*
		printf("HCLKx2 Ratio = %d, PCLK Ratio = %d \n", g_iHCLKx2_DIVN_R, g_iPCLK_DIVN_R);

		printf("============================ \n");
		printf("Current Clock Information \n");
		printf("ARMCLK: %.2fMHz  HCLKx2: %.2fMHz  HCLK: %.2fMHz  PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
		printf("============================ \n");
*/
		g_iFCLK = g_iAPLL * 1000000;
				
		Compare_Logic_DIVN();
}

//////////
// File Name : Test_DIVN_Value_Change
// File Description : This function is for clock divider test.  The clock divider Values  are changed randomly
//				 
// Input : 			
//
//						
// Output : NONE
// Version : 
void Test_DIVN_Value_Change(void)
{

	// CLK Output PAD Enable
	SYSC_CtrlCLKOUT( eCLKOUT_HCLK, 9); // for clock test, jangwj


	printf("If You Start Test, Press Any Key!!!\n");
	printf("Press 'x' : Stop Test\n\n");


	UART_Getc();

/*
	while (1)
	{
		printf("*********** TEST ************\n");
		printf("Input Operation MPLL Clock (266Mhz or 200Mhz) = ");
		iMPLL = GetIntNum();
		printf("\n");
		
		if ( iMPLL == 200 )
		{
			Data_Compare_Init();
			break;
		}
		
		if (iMPLL == 266 )
		{
			Data_Compare_Init_266();
			Setting_PMS_266();
			break;
		}
	}
*/	
	Data_Compare_Init();
	Insert_Seed();
		
	while(!UART_GetKey())
   	{
 		Test_Random_DIVN();
   	}	

   	Return_Condition();
}


void Select_PMS_Random_EVT1_1(void)
{
	g_iRandom_PMS = rand()%18;

	DisplayLED(g_iRoop3/10);
	g_iRoop3++;
	switch ( g_iRandom_PMS )
	{
		case 0:
			g_iPvalue = 6;
			g_iMvalue = 500;
			g_iSvalue = 1;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 500;						//  VCO = 1000MHz
			break;
		case 1:
			g_iPvalue = 6;
			g_iMvalue = 532;
			g_iSvalue = 1;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 532;						// VCO = 1064MHz
			break;
		case 2:
			g_iPvalue = 6;
			g_iMvalue = 550;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 275;					    // VCO = 1100MHz
			break;
		case 3:
			g_iPvalue = 6;
			g_iMvalue = 600;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 300;					// VCO = 1200MHz, for 600MHz
			break;
		case 4:
			g_iPvalue = 6;
			g_iMvalue = 650;
			g_iSvalue= 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 325;					// VCO = 1300MHz
			break;			
		case 5:
			g_iPvalue = 6;
			g_iMvalue= 700;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 350;					// VCO = 1400MHz
			break;			
		case 6:
			g_iPvalue = 6;
			g_iMvalue = 750;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 375;					// VCO = 1500MHz				
			break;			
		case 7:
			g_iPvalue = 6;
			g_iMvalue= 800;
			g_iSvalue= 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 400;					// VCO = 1600MHz
			break;			
		case 8:
			g_iPvalue = 3;
			g_iMvalue = 400;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 400;				   // VCO = 1600MHz
			break;			
		case 9:
			g_iPvalue = 3;
			g_iMvalue = 425;
			g_iSvalue = 2;
			g_iCompare_1 = g_iRandom_PMS;
			g_iAPLL = 425;				// VCO = 1700MHz
			break;			
		case 10:
			g_iPvalue = 3;
			g_iMvalue = 450;