📄 clock_test.c
字号:
break;
case 1:
printf("Selected MPLL & Selected Async Mode\n");
SYSC_ChangeMode(eASYNC_MODE);
// Clock Output pad is selected HCLK
SYSC_CtrlCLKOUT(eCLKOUT_HCLK, 4);
uRegValue0_bk = Inp32SYSC(0x10); //MPLL_CON
SYSC_SetPLL(eMPLL, uMval, uPval, uSval, uKval);
Delay(100);
break;
case 2:
printf("[Selected APLL]\n");
// Clock Output Pad is selected APLLOUT
SYSC_CtrlCLKOUT(eCLKOUT_EPLLOUT, 4);
uRegValue0_bk = Inp32SYSC(0x14); // EPLL_CON0
uRegValue1_bk = Inp32SYSC(0x18); // EPLL_CON1
SYSC_SetPLL(eEPLL, uMval, uPval, uSval, uKval);
Delay(100);
break;
}
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("Current Clock Information \n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("============================ \n");
printf("press 'q' key to exit\n");
while(UART_GetKey()!='q')
{
DisplayLED(3);
for(i=0;i<3000000;i++);
DisplayLED(9);
for(i=0;i<3000000;i++);
}
// Return the pre test value
if(uPLLType == 0 )
{
Outp32SYSC(0x10, uWA_EVT0); // W.A PLL Change 07.02.14
Outp32SYSC(0xC, uRegValue0_bk);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
}
else if (uPLLType == 1)
{
Outp32SYSC(0x10, uRegValue0_bk);
Delay(10);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
}
else if (uPLLType == 2 )
{
Outp32SYSC(0x18, uRegValue1_bk);
Outp32SYSC(0x14, uRegValue0_bk);
}
}
//////////
// File Name : Test_OnOffPll
// File Description : This function is for the PLL On/OFF
//
// Input :
//
//
// Output : NONE
// Version :
#if 0
void Test_OnOffPll(void)
{
u32 uOPType, uRegValue0_bk, uRegValue1_bk, uRegValue2_bk, uRegValue3_bk;
u32 uLockTime;
u32 i,j, uTemp, uTemp1, uTestCount;
printf("[PLL On/Off test, 10000 times]\n");
//Choose Operating Mode.
printf("\nChoose System Operating Mode : 0:Sync Mode, 1:Async Mode : ");
uOPType = GetIntNum();
//CLK_OUT Pad => HCLK
SYSC_CtrlCLKOUT(eCLKOUT_HCLK, 9);
uLockTime = 100;
SYSC_SetLockTime(eAPLL, uLockTime);
SYSC_SetLockTime(eMPLL, uLockTime);
// CLK Output PAD Enable
GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 3);
switch(uOPType)
{
case 0:
printf("[Selected Sync. Mode Operation]\n");
SYSC_ChangeMode(eSYNC_MODE);
uRegValue0_bk = Inp32SYSC(0xC); // APLL_CON
uRegValue1_bk = Inp32SYSC(0x10); // MPLL CON
uRegValue2_bk = Inp32SYSC(0x1C); // Clock Source Register
uRegValue3_bk = Inp32SYSC(0x20); // Clock Divider value
break;
case 1:
printf("Selected Async Mode Operation\n");
//SYSC_ChangeMode(eASYNC_MODE);
uRegValue0_bk = Inp32SYSC(0xC); // APLL_CON
uRegValue1_bk = Inp32SYSC(0x10); // MPLL CON
uRegValue2_bk = Inp32SYSC(0x1C); //Clock Source Register
uRegValue3_bk = Inp32SYSC(0x20); // Clock Divider value
break;
}
uTestCount = 0;
while(1)
{
if(UART_GetKey()!=0x0)
break;
if(uTestCount>100000)
break;
// if ((uTestCount%100)==0)
if ((uTestCount%10)==0)
{
DisplayLED(uTestCount/100);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("\n%d \n", uTestCount);
}
// ON&OFF Test
//for(i=0;i<10000;i++) {
//isplayLED(0x2);
uTemp = Inp32SYSC(0x20);
uTemp = (1<<12)|(0<<9)|(1<<8)|(1<<4)|(0<<0); // ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
uTemp1 = Inp32SYSC(0x1C); //Clock Source Register
uTemp1 = uTemp1 & ~(0x7) | 0x0;
Outp32SYSC(0x1C, uTemp1); // Clock Source Change
Outp32SYSC(0x20, uTemp); // Change Divide Value
SYSC_StopPLL(eAPLL);
SYSC_StopPLL(eMPLL);
Delay(10);
//DisplayLED(0x8);
SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // APLL => 400MHz
SYSC_SetPLL(eMPLL, 800, 6, 3, 0); // MPLL => 200MHz
Delay(100);
Outp32SYSC(0x20, uRegValue3_bk); // Change Divide Value
Outp32SYSC(0x1C, uRegValue2_bk); // Clock Source Change
GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 3);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
MemoryRWTest();
uTestCount++;
Delay(100);
GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 1);
}
Outp32SYSC(0xC, uRegValue0_bk);
Outp32SYSC(0x10, uRegValue1_bk);
Outp32SYSC(0x20, uRegValue3_bk);
Outp32SYSC(0x1C, uRegValue2_bk);
}
#endif
void __irq Isr_RTC_Tick1(void)
{
RTC_ClearIntP(0);
g_RTC_ALM=1;
INTC_ClearVectAddr();
}
void Test_OnOffPll(void)
{
u32 uOPType, uRegValue0_bk, uRegValue1_bk, uRegValue2_bk, uRegValue3_bk;
u32 uLockTime;
u32 uTemp, uTemp1, uTestCount;
u32 uTestTime, uTestErr;
printf("[PLL On/Off test, 10000 times]\n");
//Choose Operating Mode.
printf("\nChoose System Operating Mode : 0:Sync Mode, 1:Async Mode : ");
uOPType = GetIntNum();
//CLK_OUT Pad => HCLK
SYSC_CtrlCLKOUT(eCLKOUT_APLLOUT, 9);
uLockTime = 100;
SYSC_SetLockTime(eAPLL, uLockTime);
SYSC_SetLockTime(eMPLL, uLockTime);
// Test Point....
GPIO_SetFunctionEach(eGPIO_N, eGPIO_9, 1); // EINT9 : Output pad
switch(uOPType)
{
case 0:
printf("[Selected Sync. Mode Operation]\n");
SYSC_ChangeMode(eSYNC_MODE);
uRegValue0_bk = Inp32SYSC(0xC); // APLL_CON
uRegValue1_bk = Inp32SYSC(0x10); // MPLL CON
uRegValue2_bk = Inp32SYSC(0x1C); // Clock Source Register
uRegValue3_bk = Inp32SYSC(0x20); // Clock Divider value
break;
case 1:
printf("Selected Async Mode Operation\n");
//SYSC_ChangeMode(eASYNC_MODE);
uRegValue0_bk = Inp32SYSC(0xC); // APLL_CON
uRegValue1_bk = Inp32SYSC(0x10); // MPLL CON
uRegValue2_bk = Inp32SYSC(0x1C); //Clock Source Register
uRegValue3_bk = Inp32SYSC(0x20); // Clock Divider value
break;
}
uTestCount = 0;
uTestErr=0;
INTC_SetVectAddr(NUM_RTC_TIC,Isr_RTC_Tick1);
INTC_Enable(NUM_RTC_TIC);
uTemp = Inp32SYSC(0x20);
uTemp = (1<<12)|(0<<9)|(1<<8)|(1<<4)|(0<<0); // ARM:HCLKx2:HCLK:PCLK = 1:1:2:2
uTemp1 = Inp32SYSC(0x1C); //Clock Source Register
uTemp1 = uTemp1 & ~(0x7) | 0x0;
while(1)
{
if(UART_GetKey()!=0x0)
break;
if(uTestCount>100000)
{
printf("PLL ON/OFF Test - Test Count: %d, Error: %d\n", uTestCount, uTestErr);
break;
}
if(uTestErr>10000)
{
printf("PLL ON/OFF Fail - Test Count: %d, Error: %d\n", uTestCount, uTestErr);
break;
}
// if ((uTestCount%100)==0)
if ((uTestCount%100)==0)
{
DisplayLED(uTestCount/100);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("Test Count : %d, Error: %d \n", uTestCount, uTestErr);
UART_TxEmpty();
}
// ON&OFF Test
//for(i=0;i<10000;i++) {
//isplayLED(0x2);
g_RTC_ALM =0;
Outp32SYSC(0x1C, uTemp1); // Clock Source Change
Outp32SYSC(0x20, uTemp); // Change Divide Value
SYSC_StopPLL(eAPLL);
//Outp32SYSC(0xC, 0x0); // Temp Test
//SYSC_StopPLL(eMPLL);
//GPIO_SetDataEach(eGPIO_N, eGPIO_9, 0);
//UART_Getc();
// No Delay ~= 0.2ms
Delay(10); // Stop Time ~= 34ms
//Delay(1); // Stop Time ~=3.5ms
//Delay(200); // Stop Time ~= 667ms
//Delay(400);
GPIO_SetDataEach(eGPIO_N, eGPIO_9, 0);
//DisplayLED(0x8);
//SYSC_SetPLL(eMPLL, 800, 6, 3, 0); // MPLL => 200MHz
//SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // APLL => 400MHz , 1600MHz
//SYSC_SetPLL(eAPLL, 200, 3, 1, 0); // APLL => 400MHz , VCO 800MHz
//SYSC_SetPLL(eAPLL, 400, 2, 3, 0 ); // APLL => 300MHz, VCO 2400MHz
SYSC_SetPLL(eAPLL, 200, 3, 1, 0 ); // APLL => 300MHz, VCO 2400MHz
//SYSC_SetPLL(eAPLL, 300, 6, 1, 0); // APLL => 300MHz , VCO 600MHz
//SYSC_SetPLL(eAPLL, 800, 6, 2, 0); // APLL => 400MHz
//SYSC_SetPLL(eAPLL, 144, 1, 2, 0); // APLL => 432MHz
//SYSC_SetPLL(eAPLL, 284, 2, 2, 0); // APLL => 426MHz, 1704 => OK??
//SYSC_SetPLL(eAPLL, 288, 2, 2, 0); // APLL => 432MHz, 1728 =>
//SYSC_SetPLL(eAPLL, 170, 2, 2, 0); // APLL => 255MHz, VCO=1020MHz => OK??
//SYSC_SetPLL(eAPLL, 230, 2, 2, 0); // APLL => 345MHz, VCO 1380MHz => OK??
//SYSC_SetPLL(eAPLL, 400, 3, 5, 0); // APLL => 200MHz , 1600MHz
//SYSC_SetPLL(eAPLL, 504, 6, 5, 0); // APLL => 200MHz , 1600MHz
//SYSC_SetPLL(eAPLL, 1000, 10, 2, 0); // APLL => 300MHz
/////////////////////////// Test
//SYSC_SetPLL(eAPLL, 136, 1, 2, 0);
//SYSC_SetPLL(eAPLL, 400, 1, 4, 0); // 4800MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 2, 3, 0); // 2400MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // 1600MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 4, 2, 0); // 1200MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 5, 1, 0); // 1200MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 6, 1, 0); // 800MHz, Fout 300
//SYSC_SetPLL(eAPLL, 400, 7, 1, 0); // 685MHz, Fout 342
/////////////////////// P Divider 6
//SYSC_SetPLL(eAPLL, 300, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 402, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 404, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 406, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 408, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 410, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 412, 2, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 416, 2, 1, 0); // 800MHz
/////////////////////// P Divider 6
//SYSC_SetPLL(eAPLL, 400, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 402, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 404, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 406, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 408, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 410, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 412, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 416, 6, 1, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 200, 2, 2, 0); // 1200MHz, M/8=25, M/(Fin/P)=33.3
//SYSC_SetPLL(eAPLL, 204, 2, 2, 0); // 1224MHz, M/8=25.5, M/(Fin/P)=34
//SYSC_SetPLL(eAPLL, 208, 2, 2, 0); // 1224MHz, M/8=25.5, M/(Fin/P)=34
/////////////////////// M Divider
//SYSC_SetPLL(eAPLL, 390, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 391, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 392, 3, 2, 0); // 800MHz, => Fail
//SYSC_SetPLL(eAPLL, 393, 3, 2, 0); // 800MHz => Fail (1/8000)
//SYSC_SetPLL(eAPLL, 394, 3, 2, 0); // 800MHz = PASS
//SYSC_SetPLL(eAPLL, 395, 3, 2, 0); // 800MHz => PASS
//SYSC_SetPLL(eAPLL, 396, 3, 2, 0); // 800MHz => PASS
//SYSC_SetPLL(eAPLL, 397, 3, 2, 0); // 800MHz => PASS
//SYSC_SetPLL(eAPLL, 398, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 399, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 401, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 402, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 403, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 404, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 405, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 406, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 407, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 408, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 409, 3, 2, 0); // 800MHz
//SYSC_SetPLL(eAPLL, 410, 3, 2, 0); // 800MHz
/////////////////////// VCO Range
//SYSC_SetPLL(eAPLL, 500, 6, 1, 0); // APLL => 500MHz , 1000MHz
//SYSC_SetPLL(eAPLL, 550, 3, 3, 0); // APLL => , 2200MHz
//SYSC_SetPLL(eAPLL, 220, 3, 2, 0); // APLL => 220MHz,880MHz
//SYSC_SetPLL(eAPLL, 225, 3, 1, 0); // APLL => 450MHz, 900MHz
//SYSC_SetPLL(eAPLL, 240, 3, 2, 0); // APLL => 240MHz, 960MHz
//SYSC_SetPLL(eAPLL, 275, 3, 2, 0); // APLL => 275MHz, 1100MHz
//SYSC_SetPLL(eAPLL, 280, 3, 2, 0); // APLL => 240MHz,1120MHz
//SYSC_SetPLL(eAPLL, 284, 3, 2, 0); // 1136MHz
//SYSC_SetPLL(eAPLL, 288, 3, 2, 0); // 1152MHz
//SYSC_SetPLL(eAPLL, 292, 3, 2, 0); // 1168MHz
//SYSC_SetPLL(eAPLL, 296, 3, 2, 0); // 1184MHz
//SYSC_SetPLL(eAPLL, 312, 3, 2, 0); // 1184MHz
//SYSC_SetPLL(eAPLL, 320, 3, 2, 0); // APLL => 320MHz,1280MHz
//SYSC_SetPLL(eAPLL, 325, 3, 2, 0); // APLL => 325MHz, 1300MHz
//SYSC_SetPLL(eAPLL, 360, 3, 2, 0); // APLL => 360MHz,1440MHz
//SYSC_SetPLL(eAPLL, 375, 3, 2, 0); // APLL => 375MHz, 1500MHz
//SYSC_SetPLL(eAPLL, 390, 3, 2, 0); // APLL => 390MHz, 1560MHz
//SYSC_SetPLL(eAPLL, 395, 3, 2, 0); // APLL => 395MHz, 1580MHz
//SYSC_SetPLL(eAPLL, 399, 3, 2, 0); // APLL => 399MHz , 1596MHz
//SYSC_SetPLL(eAPLL, 402, 3, 2, 0); // APLL => 402MHz , 1608MHz
//SYSC_SetPLL(eAPLL, 405, 3, 2, 0); // APLL => 405MHz, 1620MHz
//SYSC_SetPLL(eAPLL, 410, 3, 2, 0); // APLL => 410MHz, 1640MHz
//SYSC_SetPLL(eAPLL, 425, 3, 2, 0); // APLL => 425MHz, 1700MHz
//SYSC_SetPLL(eAPLL, 440, 3, 2, 0); // APLL => 440MHz,1760MHz
//SYSC_SetPLL(eAPLL, 480, 3, 2, 0); // APLL => 480MHz,1920MHz
//SYSC_SetPLL(eAPLL, 475, 3, 2, 0); // APLL => 475MHz, 1900MHz
//SYSC_SetPLL(eAPLL, 525, 3, 2, 0); // APLL => 525MHz, 2100MHz
//SYSC_SetPLL(eAPLL, 533, 3, 2, 0); // APLL => 533MHz, 2132MHz
//SYSC_SetPLL(eAPLL, 575, 3, 3, 0); // APLL => 533MHz, 2132MHz
/////////////////////// For EVT1 Test
//SYSC_SetPLL(eAPLL, 200, 3, 2, 0); // APLL => 200MHz , 800MHz
//SYSC_SetPLL(eAPLL, 250, 3, 2, 0); // APLL => 250MHz , 1000MHz
//SYSC_SetPLL(eAPLL, 300, 3, 2, 0); // APLL => 300MHz , 1200MHz
//SYSC_SetPLL(eAPLL, 350, 3, 2, 0); // APLL => 450MHz , 1400MHz
//SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // APLL => 400MHz , 1600MHz
//SYSC_SetPLL(eAPLL, 450, 3, 2, 0); // APLL => 450MHz , 1800MHz
//SYSC_SetPLL(eAPLL, 500, 3, 2, 0); // APLL => 500MHz , 2000MHz
//Delay(50); // 1st Test ~=170ms
//Delay(1); // Test = 3ms
GPIO_SetDataEach(eGPIO_N, eGPIO_9, 1);
Outp32SYSC(0x20, uRegValue3_bk); // Change Divide Value
Outp32SYSC(0x1C, uRegValue2_bk); // Clock Source Change
Delay(100); // 100us
//UART_Getc();
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
RTC_SetCON(0,0,0,0,0,1);
RTC_SetTime(InitYEAR,InitMONTH,InitDATE,InitDAY,InitHOUR,InitMIN,InitSEC);
RTC_SetTickCNT(100);
RTC_SetCON(0,0,0,0,0,0); // Tick Clock = 128Hz?
RTC_ClearIntP(0);
StartTimer(0);
RTC_SetCON(1,0,0,0,0,1);
while(g_RTC_ALM==0);
uTestTime=StopTimer(0);
//printf("%d: uTestTime = %d \n",uTestCount, uTestTime);
RTC_SetCON(0,0,0,0,0,0);
#if 1
//if((uTestTime<4040)||(uTestTime>4100)) //Test Case (504,6,5)
//if((uTestTime<3190)||(uTestTime>3250)) //Test Case (400,3,5)
if((uTestTime<3040)||(uTestTime>3150))
//if((uTestTime<1000)||(uTestTime>1050))
{
// printf("\nTest Count : %d, Error: %d \n", uTestCount, uTestErr);
uTestErr++;
DisplayLED(0xC);
//UART_Getc();
}
#endif
//SYSC_GetClkInform();
//UART_InitDebugCh(0, 115200);
//MemoryRWTest();
// UART_Getc();
uTestCount++;
Delay(100);
//GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 1);
}
Outp32SYSC(0xC, uRegValue0_bk);
Outp32SYSC(0x10, uRegValue1_bk);
Outp32SYSC(0x20, uRegValue3_bk);
Outp32SYSC(0x1C, uRegValue2_bk);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
}
// Temp. code
void Test_OnOffPll_EVT1(void)
{
u32 uOPType, uRegValue0_bk, uRegValue1_bk, uRegValue2_bk, uRegValue3_bk;
u32 uLockTime;
u32 uTemp, uTemp1, uTestCount,uMval;
u32 uTestTime, uTestErr;
printf("[PLL On/Off test, 10000 times]\n");
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