📄 clock_test.c
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/**************************************************************************************
*
* Project Name : S3C6400 Validation
*
* Copyright 2006 by Samsung Electronics, Inc.
* All rights reserved.
*
* Project Description :
* This software is only for validating functions of the S3C6400.
* Anybody can use this software without our permission.
*
*--------------------------------------------------------------------------------------
*
* File Name : clock_test.c
*
* File Description : This file implements the test functons for the clock module
*
* Author : Wonjoon Jang
* Dept. : AP Development Team
* Created Date : 2007/01/10
* Version : 0.1
*
* History
* - Created(Wonjoon.jang 2007/01/10)
*
**************************************************************************************/
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include "option.h"
#include "library.h"
#include "sfr6400.h"
#include "system.h"
#include "gpio.h"
#include "intc.h"
#include "rtc.h"
#include "timer.h"
//#include "adcts.h"
//#include "lcd.h"
#include "sysc.h"
#include "power_test.h"
#include "clock_test.h"
//#include "dma.h"
extern volatile u32 g_TestCount;
volatile u32 g_RTC_ALM, g_TestErr, g_TestEnd;
//
volatile u32 g_iSeed, g_iNum, g_iARMCLK_DIVN_R, g_iHCLKx2_DIVN_R, g_iPCLK_DIVN_R;
volatile u32 g_iRandom_PMS;
volatile u32 g_iRoop = 0 , g_iRoop1 = 0, g_iRoop2 = 0, g_iRoop3 = 0, g_iRoop4=0, g_iRoop5=0, g_iRoop6=0, g_iRoop7 =0 ;
volatile u32 g_iPvalue, g_iMvalue, g_iSvalue;
volatile u32 g_iCompare_0 = 0, g_iCompare_1 = 0, g_iSum = 0;
volatile u32 g_iAPLL, g_iAPLL_0, g_iMPLL;
volatile u32 g_iFCLK;
//volatile u32 iDivn[16][16][16] = 0;
volatile u32 iDivn[16][16][16] = {0,};
volatile u32 iCompare_R[32] = { 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff,0x7ff, 0x7ff,
0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff, 0x7ff};
/*
volatile u32 iCompare_R[32] = { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,0xffffffff, 0xffffffff};
*/
volatile u32 iCompare_PMS[18] =
{
0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff, 0x3ffff
};
//////////
// Function Name : MemoryRWTest
// Function Description : This function test Read and Write to memory area
//
// Input :
// Output :
//
// Version : v0.1
void MemoryRWTest(void)
{
//int i;
u32 data;
u32 memError=0;
unsigned int *pt;
volatile u32 _Test_Start_Address;
volatile u32 _Test_End_Address;
//
// memory test
//
_Test_Start_Address = _DRAM_BaseAddress + 0x3000000 ;
_Test_End_Address = _DRAM_BaseAddress + 0x3010000;
printf("Memory Test(%xh-%xh):WR",_Test_Start_Address,_Test_End_Address);
pt=(unsigned int *)_Test_Start_Address;
while((unsigned int)pt<_Test_End_Address)
{
//*pt=(unsigned int)pt;
//data = (unsigned int)pt+((unsigned int)pt<<17);
data = (unsigned int)pt;
*pt=data;
//*pt=0xaaaaaaaa;
pt++;
}
printf("\b\bRD");
pt=(unsigned int *)_Test_Start_Address;
while((unsigned int)pt<_Test_End_Address)
{
data=*pt;
if(data!=(unsigned int)pt)
//if(data != 0xaaaaaaaa)
{
memError=1;
// printf("\b\bFAIL:0x%x=0x%x\n",i,data);
break;
}
*pt=0xaaaaaaaa;
pt++;
}
if(memError==0)printf("\b\bO.K.\n");
}
//////////
// Function Name : MemoryRWTest
// Function Description : This function test Read and Write to memory area
//
// Input :
// Output :
//
// Version : v0.1
bool MemoryRWTest1(u32 a0, u32 a1)
{
//int i;
u32 data;
u32 memError=0;
unsigned int *pt;
volatile u32 _Test_Start_Address;
volatile u32 _Test_End_Address;
//
// memory test
//
_Test_Start_Address = a0 ;
_Test_End_Address = a1 ;
//printf("Memory Test(%xh-%xh):WR",_Test_Start_Address,_Test_End_Address);
pt=(unsigned int *)_Test_Start_Address;
// init Data
while((unsigned int)pt<_Test_End_Address)
{
//*pt=(unsigned int)pt;
//data = (unsigned int)pt+((unsigned int)pt<<17);
data = 0;
*pt=data;
//*pt=0xaaaaaaaa;
pt++;
}
pt=(unsigned int *)_Test_Start_Address;
while((unsigned int)pt<_Test_End_Address)
{
//*pt=(unsigned int)pt;
//data = (unsigned int)pt+((unsigned int)pt<<17);
data = (unsigned int)pt;
*pt=data;
//*pt=0xaaaaaaaa;
pt++;
}
//printf("\b\bRD");
pt=(unsigned int *)_Test_Start_Address;
while((unsigned int)pt<_Test_End_Address)
{
data=*pt;
if(data!=(unsigned int)pt)
//if(data != 0xaaaaaaaa)
{
//memError=1;
memError = false;
return memError;
// printf("\b\bFAIL:0x%x=0x%x\n",i,data);
}
*pt=0xaaaaaaaa;
pt++;
}
//if(memError==0)printf("\b\bO.K.\n");
return memError;
}
//////////
// File Name : Test_Locktime
// File Description : This function is for the PLL Lock Time Test
// APLL&MPLL = 100us, EPLL = 300us
// Input :
//
//
// Output : NONE
// Version :
void Test_Locktime(void)
{
u32 uPLLType;
u32 uLockTime =300;
u32 uTestCount;
u32 uCONReg;
u32 uTestType, uLockTime0;
u32 uLockDetect0, uLockDetect1;
SYSC_ChangeMode(eASYNC_MODE);
//SYSC_ChangeSYSCLK_1(eAPLL667M, eAPLL266M , 0, 0, 3); // 667MHz, 1:4:8, ASync.. HCLKx2 = 0
SYSC_ChangeSYSCLK(eAPLL532M, eAPLL266M , 0, 0, 3);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
printf("[Lock time test ]\n");
printf("\nSelect PLL : 0:APLL, 1:MPLL, 2:EPLL : ");
uPLLType = GetIntNum();
printf("Lock time range:APLL, MPLL(100us), (EPLL)300us\n");
printf("Input Lock time[us]: ");
uLockTime = GetIntNum();
// CLK Output PAD Enable
GPIO_SetFunctionEach(eGPIO_F, eGPIO_14, 3);
switch(uPLLType)
{
case 0:
printf("[APLL Lock time test 100,000 times]\n");
printf(" Change Sync. Mode\n");
SYSC_ChangeMode(eSYNC_MODE);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
SYSC_SetLockTime( eAPLL, uLockTime);
SYSC_CtrlCLKOUT(eCLKOUT_HCLK, 9);
uLockTime0 = Inp32SYSC(0x0);
break;
case 1:
printf("[MPLL Lock time test 100,000 times]\n");
SYSC_ChangeMode(eASYNC_MODE);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
SYSC_SetLockTime( eMPLL, uLockTime);
SYSC_CtrlCLKOUT(eCLKOUT_HCLK, 9);
uLockTime0 = Inp32SYSC(0x4);
break;
case 2:
printf("[EPLL Lock time test 100,000 times]\n");
SYSC_SetLockTime( eEPLL, uLockTime);
SYSC_CtrlCLKOUT(eCLKOUT_EPLLOUT, 9);
uLockTime0 = Inp32SYSC(0x8);
break;
}
printf("\nSelect Test Type : 0:Check Lock Time, 1:for Change PLL Test : ");
uTestType = GetIntNum();
if(uTestType == 0)
{
printf("[Check Lock Time - Press any Key]\n");
GPIO_SetPullUpDownEach(eGPIO_N, eGPIO_9,0); // Pull Down Disable
GPIO_SetFunctionEach(eGPIO_N, eGPIO_9, 1); // Output Pad
//GPIO_SetDataEach(eGPIO_N, eGPIO_9,1);
Outp32(0x7f008834, 0xFFF);
GPIO_SetPullUpDownEach(eGPIO_F, eGPIO_15, 0);
GPIO_SetFunctionEach(eGPIO_F,eGPIO_15,1);
GPIO_SetDataEach(eGPIO_F,eGPIO_15,1);
while(!UART_GetKey());
//GPIO_SetDataEach(eGPIO_N, eGPIO_9,0);
//Outp32(0x7f008834, 0x0);
GPIO_SetDataEach(eGPIO_F,eGPIO_15,0);
//Delay(10);
//SYSC_SetPLL(eMPLL, 400, 3, 3,0); // EVT0
SYSC_SetPLL(eAPLL, 400, 3, 2,0); // 500MHz for PLL Change test => fail (from 400,3,2)
//SYSC_SetPLL(eMPLL, 400, 3, 3,0);
Delay(10);
GPIO_SetDataEach(eGPIO_F,eGPIO_15,1);
Outp32(0x7f008834, 0xFFF);
// GPIO_SetDataEach(eGPIO_N, eGPIO_9,1);
// Outp32SYSC(0xC,0x82140601); //532MHz, for Test 07.02.14
// Outp32SYSC(0xC,0x81900302);
//Outp32SYSC(0x1C, 0x3); // Clock Source Change => Fail....
//while(!UART_GetKey()); // for Test 07.02.14
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
uLockDetect0 = SYSC_RdLockDetect(eAPLL);
uLockDetect1= SYSC_RdLockDetect(eMPLL);
printf("\n\n");
printf("***************************************************\n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("APLL Lock : %d, MPLL_Lock: %d\n", uLockDetect0, uLockDetect1);
printf("\n");
printf(" Press any Key\n");
while(!UART_GetKey());
//GPIO_SetDataEach(eGPIO_N, eGPIO_9,0);
//Outp32(0x7f008834, 0x0);
GPIO_SetDataEach(eGPIO_F,eGPIO_15,0);
//Delay(1000);
//SYSC_SetPLL(eMPLL, 400, 3, 3,0);
SYSC_SetPLL(eAPLL, 532, 3, 2, 0); // EVT1
//SYSC_SetPLL(eMPLL, 400, 3, 3,0); // for test
Delay(10);
GPIO_SetDataEach(eGPIO_F,eGPIO_15,1);
Outp32(0x7f008834, 0xFFF);
// GPIO_SetDataEach(eGPIO_N, eGPIO_9,1);
// Outp32SYSC(0xC,0x82140601); //532MHz, for Test 07.02.14
// Outp32SYSC(0xC,0x81900302);
//Outp32SYSC(0x1C, 0x3); // Clock Source Change => Fail....
//while(!UART_GetKey()); // for Test 07.02.14
//SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
uLockDetect0 = SYSC_RdLockDetect(eAPLL);
uLockDetect1= SYSC_RdLockDetect(eMPLL);
printf("\n\n");
printf("***************************************************\n");
printf("* S3C6400 - Test firmware v0.1 *\n");
printf("***************************************************\n");
printf("System ID : Revision [%d], Pass [%d]\n", g_System_Revision, g_System_Pass);
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("APLL Lock : %d, MPLL_Lock: %d\n", uLockDetect0, uLockDetect1);
printf("\n");
}
else if(uTestType == 1)
{
printf("[Lock time test 100,000 times]\n");
while(1)
{
if(UART_GetKey()!=0x0)
break;
if(uTestCount>100000)
break;
if ((uTestCount%1000)==0)
{
DisplayLED(uTestCount%1000);
if(uPLLType == 0)
{ uCONReg = Inp32SYSC(0xC);}
else if(uPLLType == 1)
{uCONReg = Inp32SYSC(0x10);}
else if(uPLLType == 2)
{uCONReg = Inp32SYSC(0x14);}
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
printf("\n%d, PLL CON Reg: 0x%x\n", uTestCount, uCONReg);
}
if(uTestCount%2)
{
//DisplayLED(0x8);
if(uPLLType == 0 )
{
SYSC_SetPLL(eAPLL, 400, 3, 2, 0); // APLL => 400MHz
}
else if (uPLLType == 1)
{
SYSC_SetPLL(eMPLL, 800, 6, 3, 0); // MPLL => 200MHz
}
else if (uPLLType == 2 )
{
SYSC_SetPLL(eEPLL, 32, 1, 2, 0); // EPLL => 96MHz
}
Delay(10);
}
else
{
//DisplayLED(0x3);
if(uPLLType == 0 )
{
SYSC_SetPLL(eAPLL, 532, 3, 2, 0); // APLL => 532MHz, EVT1
}
else if (uPLLType == 1)
{
SYSC_SetPLL(eMPLL, 532, 3, 3, 0); // MPLL => 266MHz, EVT1
}
else if (uPLLType == 2 )
{
SYSC_SetPLL(eEPLL, 100, 3, 2, 0); // EPLL => 100MHz
}
Delay(10);
}
uTestCount++;
}
}
SYSC_ChangeMode(eASYNC_MODE);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
Delay(10);
printf("Lock Time : 0x%x\n", uLockTime0 );
printf("[PLL Lock time test %d times end]\n",uTestCount-1);
SYSC_ChangeMode(eASYNC_MODE);
//SYSC_ChangeSYSCLK_1(eAPLL667M, eAPLL266M , 0, 0, 3); // 667MHz, 1:4:8, ASync.. HCLKx2 = 0
SYSC_ChangeSYSCLK(eAPLL532M, eAPLL266M , 0, 0, 3);
SYSC_GetClkInform();
UART_InitDebugCh(0, 115200);
// Default Value肺 函版 眠啊 ?
}
//////////
// File Name : Test_ManualChangePLL
// File Description : This function is for the PLL operating
//
// Input :
//
//
// Output : NONE
// Version :
void Test_ManualChangePLL(void)
{
u32 uPLLType, uRegValue0_bk, uRegValue1_bk;
u32 uPval, uMval, uSval, uKval=0;
u32 i;
u32 uWA_EVT0, uFreq;
printf("[PLL Manual Change - This is only for test..]\n");
// Current Clock Information
SYSC_GetClkInform();
printf("Current Clock Information \n");
printf("ARMCLK: %.2fMHz HCLKx2: %.2fMHz HCLK: %.2fMHz PCLK: %.2fMHz\n",(float)g_ARMCLK/1.0e6, (float)g_HCLKx2/1.0e6, (float)g_HCLK/1.0e6, (float)g_PCLK/1.0e6);
printf("============================ \n");
printf("\nSelect PLL : 0:APLL, 1:MPLL, 2:EPLL : ");
uPLLType = GetIntNum();
printf("\nEnter the Mdiv Value( A&MPLL: 56~1023, EPLL: 13~255) : ");
uMval = GetIntNum();
printf("\nEnter the Pdiv Value( 1~63) : ");
uPval = GetIntNum();
printf("\nEnter the Sdiv Value( 0~5) : ");
uSval = GetIntNum();
if(uPLLType == 2)
{
printf("\nEnter the Kdiv Value( 0 ~ 65535) : ");
uKval = GetIntNum();
}
// CLK Output PAD Enable
switch(uPLLType)
{
case 0:
uFreq = (((FIN>>uSval)/uPval)*uMval)/1.0e6;
printf("[Selected APLL: %.2fMHz]\n", (float)uFreq);
// Clock Output Pad is selected APLLOUT
SYSC_CtrlCLKOUT(eCLKOUT_APLLOUT, 4);
uRegValue0_bk = Inp32SYSC(0xC); // APLL_CON
uWA_EVT0=Inp32SYSC(0x10); // MPLL_CON
Outp32SYSC(0x10, uWA_EVT0); // W.A : PLL Change 07.02.14
SYSC_SetPLL(eAPLL, uMval, uPval, uSval, uKval);
Delay(100);
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