📄 library.c
字号:
{"rATA_XFR_NUM ", CFCON_BASE+0x1934, 32, RW, DPDB, 0x1, 0x0},
{"rATA_XFR_CNT ", CFCON_BASE+0x1938, 32, RW, DPDB, 0x1, 0x0},
{"rATA_TBUF_START ", CFCON_BASE+0x193C, 32, RW, DPDB, 0x3, 0x0},
{"rATA_TBUF_SIZE ", CFCON_BASE+0x1940, 32, RW, DPDB, 0x1F, 0x0},
{"rATA_SBUF_START ", CFCON_BASE+0x1944, 32, RW, DPDB, 0x3, 0x0},
{"rATA_SBUF_SIZE ", CFCON_BASE+0x1948, 32, RW, DPDB, 0x1F, 0x0},
{"rATA_CADR_TBUF ", CFCON_BASE+0x194C, 32, RW, DPDB, 0x3, 0x0},
{"rATA_CADR_SBUF ", CFCON_BASE+0x1950, 32, RW, DPDB, 0x3, 0x0},
{"rATA_PIO_DTR ", CFCON_BASE+0x1954, 16, WO, DPDB, 0, 0x0},
{"rATA_PIO_FED ", CFCON_BASE+0x1958, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_SCR ", CFCON_BASE+0x195C, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_LLR ", CFCON_BASE+0x1960, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_LMR ", CFCON_BASE+0x1964, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_LHR ", CFCON_BASE+0x1968, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_DVR ", CFCON_BASE+0x196C, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_CSD ", CFCON_BASE+0x1970, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_DAD ", CFCON_BASE+0x1974, 8, WO, DPDB, 0, 0x0},
{"rATA_PIO_RDATA ", CFCON_BASE+0x197C, 16, RO, DPDB, 0, 0x0},
{"rBUS_FIFO_STATUS ", CFCON_BASE+0x1990, 19, RO, DPDB, 0, 0x0},
{"rATA_FIFO_STATUS ", CFCON_BASE+0x1994, 31, RO, DPDB, 0, 0x0},
#endif
#if 0
// Nand
{"rNFCONF ", NFCON_BASE+0x00, 32, RW, DPDB, 0, 0},
{"rNFCONT ", NFCON_BASE+0x04, 19, RW, DPDB, 0, 0},
{"rNFCMMD ", NFCON_BASE+0x08, 8 , RW, DPDB, 0, 0},
{"rNFADDR ", NFCON_BASE+0x0C, 8 , RW, DPDB, 0, 0},
{"rNFDATA ", NFCON_BASE+0x10, 32, RW, DPDB, 0, 0},
{"rNFMECCD0 ", NFCON_BASE+0x14, 32, RW, DPDB, 0, 0},
{"rNFMECCD1 ", NFCON_BASE+0x18, 32, RW, DPDB, 0, 0},
{"rNFSECCD ", NFCON_BASE+0x1C, 32, RW, DPDB, 0, 0},
{"rNFSBLK ", NFCON_BASE+0x20, 24, RW, DPDB, 0, 0},
{"rNFEBLK ", NFCON_BASE+0x24, 24, RW, DPDB, 0, 0},
{"rNFSTAT ", NFCON_BASE+0x28, 24, RW, DPDB, 0, 0},
{"rNFECCERR0 ", NFCON_BASE+0x2C, 25, RO, DPDB, 0, 0},
{"rNFECCERR1 ", NFCON_BASE+0x30, 26, RO, DPDB, 0, 0},
{"rNFMECC0 ", NFCON_BASE+0x34, 32, RO, DPDB, 0, 0},
{"rNFMECC1 ", NFCON_BASE+0x38, 24, RO, DPDB, 0, 0},
{"rNFSECC ", NFCON_BASE+0x3C, 16, RO, DPDB, 0, 0},
{"rNFMLCBITPT ", NFCON_BASE+0x40, 32, RO, DPDB, 0, 0},
// ADCTS
{"rADCCON ", ADCTS_BASE+0x00, 16, RW, DPDB, 0, 0x1FC4},
{"rADCTSC ", ADCTS_BASE+0x04, 9, RW, DPDB, 0, 0x58},
{"rADCDLY ", ADCTS_BASE+0x08, 17, RW, DPDB, 0, 0xff},
{"rADCDAT0 ", ADCTS_BASE+0x0C, 16, RO, DPDB, 0, 0x00},
{"rADCDAT1 ", ADCTS_BASE+0x10, 16, RO, DPDB, 0, 0x00},
{"rADCUPDN ", ADCTS_BASE+0x14, 2, RW, DPDB, 0, 0x0},
{"rADCCLRINT ", ADCTS_BASE+0x18, 1, WO, DPDB, 0, 0},
{"rADCCLRWK ", ADCTS_BASE+0x1C, 1, WO, DPDB, 0, 0},
// I2S0
{"rI2S0CON ", I2S0_BASE+0x00, 7, RW, DPDB, 0, 0},
{"rI2S0MOD ", I2S0_BASE+0x04, 13, RW, DPDB, 0, 0},
{"rI2S0FIC ", I2S0_BASE+0x08, 16 , RW, DPDB, 0, 0},
{"rI2S0PSR ", I2S0_BASE+0x0C, 16 , RW, DPDB, 0, 0},
{"rI2S0TXD ", I2S0_BASE+0x10, 32, WO, DPDB, 0, 0},
{"rI2S0RXD ", I2S0_BASE+0x14, 32, RO, DPDB, 0, 0},
// I2S1
{"rI2S1CON ", I2S1_BASE+0x00, 7, RW, DPDB, 0, 0},
{"rI2S1MOD ", I2S1_BASE+0x04, 13, RW, DPDB, 0, 0},
{"rI2S1FIC ", I2S1_BASE+0x08, 16 , RW, DPDB, 0, 0},
{"rI2S1PSR ", I2S1_BASE+0x0C, 16 , RW, DPDB, 0, 0},
{"rI2S1TXD ", I2S1_BASE+0x10, 32, WO, DPDB, 0, 0},
{"rI2S1RXD ", I2S1_BASE+0x14, 32, RO, DPDB, 0, 0},
//------------------ DMAC1 -----------------------------
{"rDMAC0IntStatus ", DMA0_BASE+0x00, 8, RO, DPDB, 0, 0},
{"rDMAC0IntTCStatus ", DMA0_BASE+0x04, 8, RO, DPDB, 0, 0},
{"rDMAC0IntTCClear ", DMA0_BASE+0x08, 8 , WO, DPDB, 0, 0},
{"rDMAC0IntErrorStatus ", DMA0_BASE+0x0C, 8 , RO, DPDB, 0, 0},
{"rDMAC0IntErrClr ", DMA0_BASE+0x10, 8, WO, DPDB, 0, 0},
{"rDMAC0RawIntTCStatus ", DMA0_BASE+0x14, 8, RO, DPDB, 0, 0},
{"rDMAC0RawIntErrorStatus ", DMA0_BASE+0x18, 8, RO, DPDB, 0, 0},
{"rDMAC0EnbldChns ", DMA0_BASE+0x1C, 8, RO, DPDB, 0, 0},
{"rDMAC0SoftBReq ", DMA0_BASE+0x20, 16, RW, DPDB, 0, 0},
{"rDMAC0SoftSReq ", DMA0_BASE+0x24, 16, RW, DPDB, 0, 0},
{"rDMAC0SoftLBReq ", DMA0_BASE+0x28, 16, RW, DPDB, 0, 0},
{"rDMAC0SoftLSReq ", DMA0_BASE+0x2C, 16, RW, DPDB, 0, 0},
{"rDMAC0Sync ", DMA0_BASE+0x34, 16, RW, DPDB, 0, 0},
// Ch0
{"rDMACC0SrcAddr ", DMA0_BASE+0x100, 32, RW, DPDB, 0, 0},
{"rDMACC0DestAddr ", DMA0_BASE+0x104, 32, RW, DPDB, 0, 0},
{"rDMACC0LLI ", DMA0_BASE+0x108, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC0Control0 ", DMA0_BASE+0x10C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC0Control1 ", DMA0_BASE+0x110, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC0Configuration ", DMA0_BASE+0x114, 19, RW, DPDB, 0, 0},
// Ch1
{"rDMACC1SrcAddr ", DMA0_BASE+0x120, 32, RW, DPDB, 0, 0},
{"rDMACC1DestAddr ", DMA0_BASE+0x124, 32, RW, DPDB, 0, 0},
{"rDMACC1LLI ", DMA0_BASE+0x128, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC1Control0 ", DMA0_BASE+0x12C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC1Control1 ", DMA0_BASE+0x130, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC1Configuration ", DMA0_BASE+0x134, 19, RW, DPDB, 0, 0},
// Ch2
{"rDMACC2SrcAddr ", DMA0_BASE+0x140, 32, RW, DPDB, 0, 0},
{"rDMACC2DestAddr ", DMA0_BASE+0x144, 32, RW, DPDB, 0, 0},
{"rDMACC2LLI ", DMA0_BASE+0x148, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC2Control0 ", DMA0_BASE+0x14C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC2Control1 ", DMA0_BASE+0x150, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC2Configuration ", DMA0_BASE+0x154, 19, RW, DPDB, 0, 0},
// Ch3
{"rDMACC3SrcAddr ", DMA0_BASE+0x160, 32, RW, DPDB, 0, 0},
{"rDMACC3DestAddr ", DMA0_BASE+0x164, 32, RW, DPDB, 0, 0},
{"rDMACC3LLI ", DMA0_BASE+0x168, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC3Control0 ", DMA0_BASE+0x16C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC3Control1 ", DMA0_BASE+0x170, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC3Configuration ", DMA0_BASE+0x174, 19, RW, DPDB, 0, 0},
// Ch4
{"rDMACC4SrcAddr ", DMA0_BASE+0x180, 32, RW, DPDB, 0, 0},
{"rDMACC4DestAddr ", DMA0_BASE+0x184, 32, RW, DPDB, 0, 0},
{"rDMACC4LLI ", DMA0_BASE+0x188, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC4Control0 ", DMA0_BASE+0x18C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC4Control1 ", DMA0_BASE+0x190, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC4Configuration ", DMA0_BASE+0x194, 19, RW, DPDB, 0, 0},
// Ch5
{"rDMACC5SrcAddr ", DMA0_BASE+0x1A0, 32, RW, DPDB, 0, 0},
{"rDMACC5DestAddr ", DMA0_BASE+0x1A4, 32, RW, DPDB, 0, 0},
{"rDMACC5LLI ", DMA0_BASE+0x1A8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC5Control0 ", DMA0_BASE+0x1AC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC5Control1 ", DMA0_BASE+0x1B0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC5Configuration ", DMA0_BASE+0x1B4, 19, RW, DPDB, 0, 0},
// Ch6
{"rDMACC6SrcAddr ", DMA0_BASE+0x1C0, 32, RW, DPDB, 0, 0},
{"rDMACC6DestAddr ", DMA0_BASE+0x1C4, 32, RW, DPDB, 0, 0},
{"rDMACC6LLI ", DMA0_BASE+0x1C8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC6Control0 ", DMA0_BASE+0x1CC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC6Control1 ", DMA0_BASE+0x1D0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC6Configuration ", DMA0_BASE+0x1D4, 19, RW, DPDB, 0, 0},
// Ch7
{"rDMACC7SrcAddr ", DMA0_BASE+0x1E0, 32, RW, DPDB, 0, 0},
{"rDMACC7DestAddr ", DMA0_BASE+0x1E4, 32, RW, DPDB, 0, 0},
{"rDMACC7LLI ", DMA0_BASE+0x1E8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMACC7Control0 ", DMA0_BASE+0x1EC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMACC7Control1 ", DMA0_BASE+0x1F0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMACC7Configuration ", DMA0_BASE+0x1F4, 19, RW, DPDB, 0, 0},
{"rDMAC0Configuration ", DMA0_BASE+0x30, 3, RW, DPDB, 0, 0},
//------------------ DMAC1 -----------------------------
{"rDMAC1IntStatus ", DMA1_BASE+0x00, 8, RO, DPDB, 0, 0},
{"rDMAC1IntTCStatus ", DMA1_BASE+0x04, 8, RO, DPDB, 0, 0},
{"rDMAC1IntTCClear ", DMA1_BASE+0x08, 8 , WO, DPDB, 0, 0},
{"rDMAC1IntErrorStatus ", DMA1_BASE+0x0C, 8 , RO, DPDB, 0, 0},
{"rDMAC1IntErrClr ", DMA1_BASE+0x10, 8, WO, DPDB, 0, 0},
{"rDMAC1RawIntTCStatus ", DMA1_BASE+0x14, 8, RO, DPDB, 0, 0},
{"rDMAC1RawIntErrorStatus ", DMA1_BASE+0x18, 8, RO, DPDB, 0, 0},
{"rDMAC1EnbldChns ", DMA1_BASE+0x1C, 8, RO, DPDB, 0, 0},
{"rDMAC1SoftBReq ", DMA1_BASE+0x20, 16, RW, DPDB, 0, 0},
{"rDMAC1SoftSReq ", DMA1_BASE+0x24, 16, RW, DPDB, 0, 0},
{"rDMAC1SoftLBReq ", DMA1_BASE+0x28, 16, RW, DPDB, 0, 0},
{"rDMAC1SoftLSReq ", DMA1_BASE+0x2C, 16, RW, DPDB, 0, 0},
{"rDMAC1Sync ", DMA1_BASE+0x34, 16, RW, DPDB, 0, 0},
// Ch0
{"rDMAC1C0SrcAddr ", DMA1_BASE+0x100, 32, RW, DPDB, 0, 0},
{"rDMAC1C0DestAddr ", DMA1_BASE+0x104, 32, RW, DPDB, 0, 0},
{"rDMAC1C0LLI ", DMA1_BASE+0x108, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C0Control0 ", DMA1_BASE+0x10C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C0Control1 ", DMA1_BASE+0x110, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C0Configuration ", DMA1_BASE+0x114, 19, RW, DPDB, 0, 0},
// Ch1
{"rDMAC1C1SrcAddr ", DMA1_BASE+0x120, 32, RW, DPDB, 0, 0},
{"rDMAC1C1DestAddr ", DMA1_BASE+0x124, 32, RW, DPDB, 0, 0},
{"rDMAC1C1LLI ", DMA1_BASE+0x128, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C1Control0 ", DMA1_BASE+0x12C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C1Control1 ", DMA1_BASE+0x130, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C1Configuration ", DMA1_BASE+0x134, 19, RW, DPDB, 0, 0},
// Ch2
{"rDMAC1C2SrcAddr ", DMA1_BASE+0x140, 32, RW, DPDB, 0, 0},
{"rDMAC1C2DestAddr ", DMA1_BASE+0x144, 32, RW, DPDB, 0, 0},
{"rDMAC1C2LLI ", DMA1_BASE+0x148, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C2Control0 ", DMA1_BASE+0x14C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C2Control1 ", DMA1_BASE+0x150, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C2Configuration ", DMA1_BASE+0x154, 19, RW, DPDB, 0, 0},
// Ch3
{"rDMAC1C3SrcAddr ", DMA1_BASE+0x160, 32, RW, DPDB, 0, 0},
{"rDMAC1C3DestAddr ", DMA1_BASE+0x164, 32, RW, DPDB, 0, 0},
{"rDMAC1C3LLI ", DMA1_BASE+0x168, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C3Control0 ", DMA1_BASE+0x16C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C3Control1 ", DMA1_BASE+0x170, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C3Configuration ", DMA1_BASE+0x174, 19, RW, DPDB, 0, 0},
// Ch4
{"rDMAC1C4SrcAddr ", DMA1_BASE+0x180, 32, RW, DPDB, 0, 0},
{"rDMAC1C4DestAddr ", DMA1_BASE+0x184, 32, RW, DPDB, 0, 0},
{"rDMAC1C4LLI ", DMA1_BASE+0x188, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C4Control0 ", DMA1_BASE+0x18C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C4Control1 ", DMA1_BASE+0x190, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C4Configuration ", DMA1_BASE+0x194, 19, RW, DPDB, 0, 0},
// Ch5
{"rDMAC1C5SrcAddr ", DMA1_BASE+0x1A0, 32, RW, DPDB, 0, 0},
{"rDMAC1C5DestAddr ", DMA1_BASE+0x1A4, 32, RW, DPDB, 0, 0},
{"rDMAC1C5LLI ", DMA1_BASE+0x1A8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C5Control0 ", DMA1_BASE+0x1AC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C5Control1 ", DMA1_BASE+0x1B0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C5Configuration ", DMA1_BASE+0x1B4, 19, RW, DPDB, 0, 0},
// Ch6
{"rDMAC1C6SrcAddr ", DMA1_BASE+0x1C0, 32, RW, DPDB, 0, 0},
{"rDMAC1C6DestAddr ", DMA1_BASE+0x1C4, 32, RW, DPDB, 0, 0},
{"rDMAC1C6LLI ", DMA1_BASE+0x1C8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C6Control0 ", DMA1_BASE+0x1CC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C6Control1 ", DMA1_BASE+0x1D0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C6Configuration ", DMA1_BASE+0x1D4, 19, RW, DPDB, 0, 0},
// Ch7
{"rDMAC1C7SrcAddr ", DMA1_BASE+0x1E0, 32, RW, DPDB, 0, 0},
{"rDMAC1C7DestAddr ", DMA1_BASE+0x1E4, 32, RW, DPDB, 0, 0},
{"rDMAC1C7LLI ", DMA1_BASE+0x1E8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rDMAC1C7Control0 ", DMA1_BASE+0x1EC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rDMAC1C7Control1 ", DMA1_BASE+0x1F0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rDMAC1C7Configuration ", DMA1_BASE+0x1F4, 19, RW, DPDB, 0, 0},
{"rDMAC1Configuration ", DMA1_BASE+0x30, 3, RW, DPDB, 0, 0},
//------------------ SDMAC0 -----------------------------
{"rSDMAC0IntStatus ", SDMA0_BASE+0x00, 8, RO, DPDB, 0, 0},
{"rSDMAC0IntTCStatus ", SDMA0_BASE+0x04, 8, RO, DPDB, 0, 0},
{"rSDMAC0IntTCClear ", SDMA0_BASE+0x08, 8 , WO, DPDB, 0, 0},
{"rSDMAC0IntErrorStatus ", SDMA0_BASE+0x0C, 8 , RO, DPDB, 0, 0},
{"rSDMAC0IntErrClr ", SDMA0_BASE+0x10, 8, WO, DPDB, 0, 0},
{"rSDMAC0RawIntTCStatus ", SDMA0_BASE+0x14, 8, RO, DPDB, 0, 0},
{"rSDMAC0RawIntErrorStatus ", SDMA0_BASE+0x18, 8, RO, DPDB, 0, 0},
{"rSDMAC0EnbldChns ", SDMA0_BASE+0x1C, 8, RO, DPDB, 0, 0},
{"rSDMAC0SoftBReq ", SDMA0_BASE+0x20, 16, RW, DPDB, 0, 0},
{"rSDMAC0SoftSReq ", SDMA0_BASE+0x24, 16, RW, DPDB, 0, 0},
{"rSDMAC0SoftLBReq ", SDMA0_BASE+0x28, 16, RW, DPDB, 0, 0},
{"rSDMAC0SoftLSReq ", SDMA0_BASE+0x2C, 16, RW, DPDB, 0, 0},
{"rSDMAC0Sync ", SDMA0_BASE+0x34, 16, RW, DPDB, 0, 0},
// Ch0
{"rSDMAC0C0SrcAddr ", SDMA0_BASE+0x100, 32, RW, DPDB, 0, 0},
{"rSDMAC0C0DestAddr ", SDMA0_BASE+0x104, 32, RW, DPDB, 0, 0},
{"rSDMAC0C0LLI ", SDMA0_BASE+0x108, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C0Control0 ", SDMA0_BASE+0x10C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C0Control1 ", SDMA0_BASE+0x110, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C0Configuration", SDMA0_BASE+0x114, 19, RW, DPDB, 0, 0},
// Ch1
{"rSDMAC0C1SrcAddr ", SDMA0_BASE+0x120, 32, RW, DPDB, 0, 0},
{"rSDMAC0C1DestAddr ", SDMA0_BASE+0x124, 32, RW, DPDB, 0, 0},
{"rSDMAC0C1LLI ", SDMA0_BASE+0x128, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C1Control0 ", SDMA0_BASE+0x12C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C1Control1 ", SDMA0_BASE+0x130, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C1Configuration", SDMA0_BASE+0x134, 19, RW, DPDB, 0, 0},
// Ch2
{"rSDMAC0C2SrcAddr ", SDMA0_BASE+0x140, 32, RW, DPDB, 0, 0},
{"rSDMAC0C2DestAddr ", SDMA0_BASE+0x144, 32, RW, DPDB, 0, 0},
{"rSDMAC0C2LLI ", SDMA0_BASE+0x148, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C2Control0 ", SDMA0_BASE+0x14C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C2Control1 ", SDMA0_BASE+0x150, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C2Configuration", SDMA0_BASE+0x154, 19, RW, DPDB, 0, 0},
// Ch3
{"rSDMAC0C3SrcAddr ", SDMA0_BASE+0x160, 32, RW, DPDB, 0, 0},
{"rSDMAC0C3DestAddr ", SDMA0_BASE+0x164, 32, RW, DPDB, 0, 0},
{"rSDMAC0C3LLI ", SDMA0_BASE+0x168, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C3Control0 ", SDMA0_BASE+0x16C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C3Control1 ", SDMA0_BASE+0x170, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C3Configuration", SDMA0_BASE+0x174, 19, RW, DPDB, 0, 0},
// Ch4
{"rSDMAC0C4SrcAddr ", SDMA0_BASE+0x180, 32, RW, DPDB, 0, 0},
{"rSDMAC0C4DestAddr ", SDMA0_BASE+0x184, 32, RW, DPDB, 0, 0},
{"rSDMAC0C4LLI ", SDMA0_BASE+0x188, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C4Control0 ", SDMA0_BASE+0x18C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C4Control1 ", SDMA0_BASE+0x190, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C4Configuration", SDMA0_BASE+0x194, 19, RW, DPDB, 0, 0},
// Ch5
{"rSDMAC0C5SrcAddr ", SDMA0_BASE+0x1A0, 32, RW, DPDB, 0, 0},
{"rSDMAC0C5DestAddr ", SDMA0_BASE+0x1A4, 32, RW, DPDB, 0, 0},
{"rSDMAC0C5LLI ", SDMA0_BASE+0x1A8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C5Control0 ", SDMA0_BASE+0x1AC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C5Control1 ", SDMA0_BASE+0x1B0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C5Configuration", SDMA0_BASE+0x1B4, 19, RW, DPDB, 0, 0},
// Ch6
{"rSDMAC0C6SrcAddr ", SDMA0_BASE+0x1C0, 32, RW, DPDB, 0, 0},
{"rSDMAC0C6DestAddr ", SDMA0_BASE+0x1C4, 32, RW, DPDB, 0, 0},
{"rSDMAC0C6LLI ", SDMA0_BASE+0x1C8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C6Control0 ", SDMA0_BASE+0x1CC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C6Control1 ", SDMA0_BASE+0x1D0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C6Configuration", SDMA0_BASE+0x1D4, 19, RW, DPDB, 0, 0},
// Ch7
{"rSDMAC0C7SrcAddr ", SDMA0_BASE+0x1E0, 32, RW, DPDB, 0, 0},
{"rSDMAC0C7DestAddr ", SDMA0_BASE+0x1E4, 32, RW, DPDB, 0, 0},
{"rSDMAC0C7LLI ", SDMA0_BASE+0x1E8, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC0C7Control0 ", SDMA0_BASE+0x1EC, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC0C7Control1 ", SDMA0_BASE+0x1F0, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC0C7Configuration", SDMA0_BASE+0x1F4, 19, RW, DPDB, 0, 0},
{"rSDMAC0Configuration ", SDMA0_BASE+0x30, 3, RW, DPDB, 0, 0},
//------------------ SDMAC1 -----------------------------
{"rSDMAC1IntStatus ", SDMA1_BASE+0x00, 8, RO, DPDB, 0, 0},
{"rSDMAC1IntTCStatus ", SDMA1_BASE+0x04, 8, RO, DPDB, 0, 0},
{"rSDMAC1IntTCClear ", SDMA1_BASE+0x08, 8 , WO, DPDB, 0, 0},
{"rSDMAC1IntErrorStatus ", SDMA1_BASE+0x0C, 8 , RO, DPDB, 0, 0},
{"rSDMAC1IntErrClr ", SDMA1_BASE+0x10, 8, WO, DPDB, 0, 0},
{"rSDMAC1RawIntTCStatus ", SDMA1_BASE+0x14, 8, RO, DPDB, 0, 0},
{"rSDMAC1RawIntErrorStatus ", SDMA1_BASE+0x18, 8, RO, DPDB, 0, 0},
{"rSDMAC1EnbldChns ", SDMA1_BASE+0x1C, 8, RO, DPDB, 0, 0},
{"rSDMAC1SoftBReq ", SDMA1_BASE+0x20, 16, RW, DPDB, 0, 0},
{"rSDMAC1SoftSReq ", SDMA1_BASE+0x24, 16, RW, DPDB, 0, 0},
{"rSDMAC1SoftLBReq ", SDMA1_BASE+0x28, 16, RW, DPDB, 0, 0},
{"rSDMAC1SoftLSReq ", SDMA1_BASE+0x2C, 16, RW, DPDB, 0, 0},
{"rSDMAC1Sync ", SDMA1_BASE+0x34, 16, RW, DPDB, 0, 0},
// Ch0
{"rSDMAC1C0SrcAddr ", SDMA1_BASE+0x100, 32, RW, DPDB, 0, 0},
{"rSDMAC1C0DestAddr ", SDMA1_BASE+0x104, 32, RW, DPDB, 0, 0},
{"rSDMAC1C0LLI ", SDMA1_BASE+0x108, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC1C0Control0 ", SDMA1_BASE+0x10C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC1C0Control1 ", SDMA1_BASE+0x110, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC1C0Configuration", SDMA1_BASE+0x114, 19, RW, DPDB, 0, 0},
// Ch1
{"rSDMAC1C1SrcAddr ", SDMA1_BASE+0x120, 32, RW, DPDB, 0, 0},
{"rSDMAC1C1DestAddr ", SDMA1_BASE+0x124, 32, RW, DPDB, 0, 0},
{"rSDMAC1C1LLI ", SDMA1_BASE+0x128, 32, RW, DPPB, 0xFFFFFFFD, 0},
{"rSDMAC1C1Control0 ", SDMA1_BASE+0x12C, 32, RW, DPPB, 0xFFFFF000, 0},
{"rSDMAC1C1Control1 ", SDMA1_BASE+0x130, 25, RW, DPPB, 0x0, 0}, // not WO, but this register acts like WO.
{"rSDMAC1C1Configuration", SDMA1_BASE+0x134, 19, RW, DPDB, 0, 0},
// Ch2
{"rSDMAC1C2SrcAddr ", SDMA1_BASE+0x140, 32, RW, DPDB, 0, 0},
{"rSDMAC1C2DestAddr ", SDMA1_BASE+0x144, 32, RW, DPDB, 0, 0},
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