dataflash.h

AT91BootSAM9261.zip,atmelsam9261微处理器启动初始化源代码

//*---------------------------------------------------------------------------
//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*---------------------------------------------------------------------------
//* File Name           : AT91_SpiDataFlash.h
//* Object              : Data Flash Atmel Description File
//* Translator          :
//*---------------------------------------------------------------------------

#ifndef _DataFlash_h
#define _DataFlash_h

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef AT91SAM9260
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(4*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM_1
// SPI CLOCK
#define AT91C_SPI_CLK 				1000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xd << 16)	// 250ns min (tCSS) <=> 13/50000000 = 260ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> 32/50000000 + SCBR/(2*50000000) > 640 ns

#endif

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef AT91SAM9261
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(156*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xc << 16)	// 250ns min (tCSS) <=> 12/48000000 = 250ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000)

#endif
////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef AT91SAM9262
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(76*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xc << 16)	// 250ns min (tCSS) <=> 12/48000000 = 250ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000)

#endif
////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef AT91C340

// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(156*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM_2
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xc << 16)	// 250ns min (tCSS) <=> 12/48000000 = 250ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000)

#endif
////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef M9261
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(156*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xc << 16)	// 250ns min (tCSS) <=> 12/48000000 = 250ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000)
#endif
////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef MISTRAL9261
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(28*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_IRAM
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0x9 << 16)	// 250ns min (tCSS) <=> 9/33330000 = 270ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*33330000)
#endif
////////////////////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////////////////////
#ifdef AT91RM9200
// memory size max for the application area in SRAM
#define AT91C_MEMORY_SIZE			(12*1024)
// base address for uploading and downloading
#define AT91C_BASE_LOAD_ADDRESS		AT91C_ISRAM
// SPI CLOCK
#define AT91C_SPI_CLK 				8000000
// AC characteristics
// DLYBS = tCSS= 250ns min and DLYBCT = tCSH = 250ns
#define DATAFLASH_TCSS				(0xc << 16)	// 250ns min (tCSS) <=> 12/48000000 = 250ns
#define DATAFLASH_TCHS				(0x1 << 24)	// 250ns min (tCSH) <=> (64*1+SCBR)/(2*48000000)
#endif
////////////////////////////////////////////////////////////////////////////////////////////////

// Chip Select 0 : NPCS0 %1110
#define AT91C_SPI_PCS0_DATAFLASH	0xE
// Chip Select 1 : NPCS1 %1101
#define AT91C_SPI_PCS1_DATAFLASH	0xD


// Max PDC Size for SPI Continuous Read
#define AT91C_MAX_PDC_SIZE	0xFFFF

////////////////////////////////////////////////////////////////////////////////////////////////
// DataFlash Structures
////////////////////////////////////////////////////////////////////////////////////////////////

/*---------------------------------------------*/
/* DataFlash Descriptor Structure Definition   */
/*---------------------------------------------*/
typedef struct _AT91S_DataflashDesc {
	unsigned char 			*tx_cmd_pt;
	unsigned int 			tx_cmd_size;
	unsigned char 			*rx_cmd_pt;
	unsigned int 			rx_cmd_size;
	unsigned char 			*tx_data_pt;
	unsigned int 			tx_data_size;
	unsigned char 			*rx_data_pt;
	unsigned int 			rx_data_size;
	volatile unsigned char 	state;
	volatile unsigned char 	DataFlash_state;
	unsigned char 			command[8];
} AT91S_DataflashDesc, *AT91PS_DataflashDesc;

/*---------------------------------------------*/
/* DataFlash device definition structure       */
/*---------------------------------------------*/
typedef struct _AT91S_Dataflash {
	int pages_number;			/* dataflash page number */
	int pages_size;				/* dataflash page size */
	int page_offset;			/* page offset in command */
} AT91S_DataflashFeatures, *AT91PS_DataflashFeatures;


/*---------------------------------------------*/
/* DataFlash Structure Definition	       */
/*---------------------------------------------*/
typedef struct _AT91S_DataFlash {
	AT91S_DataflashDesc 		DataFlashDesc;	/* dataflash descriptor */
	AT91S_DataflashFeatures 	Device;		/* Pointer on a dataflash features array */
	unsigned int 				id;				/* device id */
} AT91S_DataFlash, *AT91PS_DataFlash;

////////////////////////////////////////////////////////////////////////////////////////////////
// DataFlash Misc
////////////////////////////////////////////////////////////////////////////////////////////////

#define AT45DB011B		0x0C
#define AT45DB021B		0x14
#define AT45DB041B		0x1C
#define AT45DB081B		0x24
#define AT45DB161B		0x2C
#define AT45DB321B		0x34
#define AT45DB642		0x3C
#define AT45DB1282		0x10
#define AT45DB2562		0x18
#define AT45DB5122		0x20

#define AT91C_DATAFLASH_TIMEOUT			10000000

/* DataFlash return value */
#define AT91C_DATAFLASH_BUSY			0x00
#define AT91C_DATAFLASH_OK				0x01
#define AT91C_DATAFLASH_ERROR			0x02
#define AT91C_DATAFLASH_MEMORY_OVERFLOW	0x03

/* Driver State */
#define IDLE		0x0
#define BUSY		0x1
#define ERROR		0x2
#define GET_STATUS	0x0F

////////////////////////////////////////////////////////////////////////////////////////////////
// Command Definition
////////////////////////////////////////////////////////////////////////////////////////////////

/* READ COMMANDS */
#define DB_CONTINUOUS_ARRAY_READ	0xE8	/* Continuous array read */
#define DB_STATUS					0xD7	/* Status Register */

#endif