tioce.h

LINUX 2.6.17.4的源码

	/* Response Queue */
	u64	ce_ure_maint_rspq[64];	    /* 0x01BA00 -- 0x01BBF8 */

	u64	ce_pad_01C000[4224];	    /* 0x01BC00 -- 0x023FF8 */

	/* Admin Build-a-Packet Buffer */
	struct	ce_adm_maint_bap_buf_data {
		u64	data63_0[258];	    /* 0x024000 -- 0x024808 */
		u64	data127_64[258];    /* 0x024810 -- 0x025018 */
		u64	parity[258];	    /* 0x025020 -- 0x025828 */
	} ce_adm_maint_bap_buf;

	u64	ce_pad_025830[5370];	    /* 0x025830 -- 0x02FFF8 */

	/* URE: 40bit PMU ATE Buffer */		    /* 0x030000 -- 0x037FF8 */
	u64	ce_ure_ate40[TIOCE_NUM_M40_ATES];

	/* URE: 32/40bit PMU ATE Buffer */	    /* 0x038000 -- 0x03BFF8 */
	u64	ce_ure_ate3240[TIOCE_NUM_M3240_ATES];

	u64	ce_pad_03C000[2050];	    /* 0x03C000 -- 0x040008 */

	/*
	 * DRE: Down Stream Request Engine
         */
	u64	ce_dre_dyn_credit_status1;		/* 0x040010 */
	u64	ce_dre_dyn_credit_status2;		/* 0x040018 */
	u64	ce_dre_last_credit_status1;		/* 0x040020 */
	u64	ce_dre_last_credit_status2;		/* 0x040028 */
	u64	ce_dre_credit_limit1;			/* 0x040030 */
	u64	ce_dre_credit_limit2;			/* 0x040038 */
	u64	ce_dre_force_credit1;			/* 0x040040 */
	u64	ce_dre_force_credit2;			/* 0x040048 */
	u64	ce_dre_debug_mux1;			/* 0x040050 */
	u64	ce_dre_debug_mux2;			/* 0x040058 */
	u64	ce_dre_ssp_err_cmd_wrd;			/* 0x040060 */
	u64	ce_dre_ssp_err_addr;			/* 0x040068 */
	u64	ce_dre_comp_err_cmd_wrd;		/* 0x040070 */
	u64	ce_dre_comp_err_addr;			/* 0x040078 */
	u64	ce_dre_req_status;			/* 0x040080 */
	u64	ce_dre_config1;				/* 0x040088 */
	u64	ce_dre_config2;				/* 0x040090 */
	u64	ce_dre_config_req_status;		/* 0x040098 */
	u64	ce_pad_0400A0[12];	    /* 0x0400A0 -- 0x0400F8 */
	u64	ce_dre_dyn_fifo;			/* 0x040100 */
	u64	ce_pad_040108[3];	    /* 0x040108 -- 0x040118 */
	u64	ce_dre_last_fifo;			/* 0x040120 */

	u64	ce_pad_040128[27];	    /* 0x040128 -- 0x0401F8 */

	/* DRE Downstream Head Queue */
	struct	ce_dre_maint_ds_head_queue {
		u64	data63_0[32];	    /* 0x040200 -- 0x0402F8 */
		u64	data127_64[32];	    /* 0x040300 -- 0x0403F8 */
		u64	parity[32];	    /* 0x040400 -- 0x0404F8 */
	} ce_dre_maint_ds_head_q;

	u64	ce_pad_040500[352];	    /* 0x040500 -- 0x040FF8 */

	/* DRE Downstream Data Queue */
	struct	ce_dre_maint_ds_data_queue {
		u64	data63_0[256];	    /* 0x041000 -- 0x0417F8 */
		u64	ce_pad_041800[256]; /* 0x041800 -- 0x041FF8 */
		u64	data127_64[256];    /* 0x042000 -- 0x0427F8 */
		u64	ce_pad_042800[256]; /* 0x042800 -- 0x042FF8 */
		u64	parity[256];	    /* 0x043000 -- 0x0437F8 */
		u64	ce_pad_043800[256]; /* 0x043800 -- 0x043FF8 */
	} ce_dre_maint_ds_data_q;

	/* DRE URE Upstream Response Queue */
	struct	ce_dre_maint_ure_us_rsp_queue {
		u64	data63_0[8];	    /* 0x044000 -- 0x044038 */
		u64	ce_pad_044040[24];  /* 0x044040 -- 0x0440F8 */
		u64	data127_64[8];      /* 0x044100 -- 0x044138 */
		u64	ce_pad_044140[24];  /* 0x044140 -- 0x0441F8 */
		u64	parity[8];	    /* 0x044200 -- 0x044238 */
		u64	ce_pad_044240[24];  /* 0x044240 -- 0x0442F8 */
	} ce_dre_maint_ure_us_rsp_q;

	u64 	ce_dre_maint_us_wrt_rsp[32];/* 0x044300 -- 0x0443F8 */

	u64	ce_end_of_struct;			/* 0x044400 */
} tioce_t;

/* ce_lsiX_gb_cfg1 register bit masks & shifts */
#define CE_LSI_GB_CFG1_RXL0S_THS_SHFT	0
#define CE_LSI_GB_CFG1_RXL0S_THS_MASK	(0xffULL << 0)
#define CE_LSI_GB_CFG1_RXL0S_SMP_SHFT	8
#define CE_LSI_GB_CFG1_RXL0S_SMP_MASK	(0xfULL << 8);
#define CE_LSI_GB_CFG1_RXL0S_ADJ_SHFT	12
#define CE_LSI_GB_CFG1_RXL0S_ADJ_MASK	(0x7ULL << 12)
#define CE_LSI_GB_CFG1_RXL0S_FLT_SHFT	15
#define CE_LSI_GB_CFG1_RXL0S_FLT_MASK	(0x1ULL << 15)
#define CE_LSI_GB_CFG1_LPBK_SEL_SHFT	16
#define CE_LSI_GB_CFG1_LPBK_SEL_MASK	(0x3ULL << 16)
#define CE_LSI_GB_CFG1_LPBK_EN_SHFT	18
#define CE_LSI_GB_CFG1_LPBK_EN_MASK	(0x1ULL << 18)
#define CE_LSI_GB_CFG1_RVRS_LB_SHFT	19
#define CE_LSI_GB_CFG1_RVRS_LB_MASK	(0x1ULL << 19)
#define CE_LSI_GB_CFG1_RVRS_CLK_SHFT	20
#define CE_LSI_GB_CFG1_RVRS_CLK_MASK	(0x3ULL << 20)
#define CE_LSI_GB_CFG1_SLF_TS_SHFT	24
#define CE_LSI_GB_CFG1_SLF_TS_MASK	(0xfULL << 24)

/* ce_adm_int_mask/ce_adm_int_status register bit defines */
#define CE_ADM_INT_CE_ERROR_SHFT		0
#define CE_ADM_INT_LSI1_IP_ERROR_SHFT		1
#define CE_ADM_INT_LSI2_IP_ERROR_SHFT		2
#define CE_ADM_INT_PCIE_ERROR_SHFT		3
#define CE_ADM_INT_PORT1_HOTPLUG_EVENT_SHFT	4
#define CE_ADM_INT_PORT2_HOTPLUG_EVENT_SHFT	5
#define CE_ADM_INT_PCIE_PORT1_DEV_A_SHFT	6
#define CE_ADM_INT_PCIE_PORT1_DEV_B_SHFT	7
#define CE_ADM_INT_PCIE_PORT1_DEV_C_SHFT	8
#define CE_ADM_INT_PCIE_PORT1_DEV_D_SHFT	9
#define CE_ADM_INT_PCIE_PORT2_DEV_A_SHFT	10
#define CE_ADM_INT_PCIE_PORT2_DEV_B_SHFT	11
#define CE_ADM_INT_PCIE_PORT2_DEV_C_SHFT	12
#define CE_ADM_INT_PCIE_PORT2_DEV_D_SHFT	13
#define CE_ADM_INT_PCIE_MSG_SHFT		14 /*see int_dest_14*/
#define CE_ADM_INT_PCIE_MSG_SLOT_0_SHFT		14
#define CE_ADM_INT_PCIE_MSG_SLOT_1_SHFT		15
#define CE_ADM_INT_PCIE_MSG_SLOT_2_SHFT		16
#define CE_ADM_INT_PCIE_MSG_SLOT_3_SHFT		17
#define CE_ADM_INT_PORT1_PM_PME_MSG_SHFT	22
#define CE_ADM_INT_PORT2_PM_PME_MSG_SHFT	23

/* ce_adm_force_int register bit defines */
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_A_SHFT	0
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_B_SHFT	1
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_C_SHFT	2
#define CE_ADM_FORCE_INT_PCIE_PORT1_DEV_D_SHFT	3
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_A_SHFT	4
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_B_SHFT	5
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_C_SHFT	6
#define CE_ADM_FORCE_INT_PCIE_PORT2_DEV_D_SHFT	7
#define CE_ADM_FORCE_INT_ALWAYS_SHFT		8

/* ce_adm_int_dest register bit masks & shifts */
#define INTR_VECTOR_SHFT			56

/* ce_adm_error_mask and ce_adm_error_summary register bit masks */
#define CE_ADM_ERR_CRM_SSP_REQ_INVALID			(0x1ULL <<  0)
#define CE_ADM_ERR_SSP_REQ_HEADER			(0x1ULL <<  1)
#define CE_ADM_ERR_SSP_RSP_HEADER			(0x1ULL <<  2)
#define CE_ADM_ERR_SSP_PROTOCOL_ERROR			(0x1ULL <<  3)
#define CE_ADM_ERR_SSP_SBE				(0x1ULL <<  4)
#define CE_ADM_ERR_SSP_MBE				(0x1ULL <<  5)
#define CE_ADM_ERR_CXM_CREDIT_OFLOW			(0x1ULL <<  6)
#define CE_ADM_ERR_DRE_SSP_REQ_INVAL			(0x1ULL <<  7)
#define CE_ADM_ERR_SSP_REQ_LONG				(0x1ULL <<  8)
#define CE_ADM_ERR_SSP_REQ_OFLOW			(0x1ULL <<  9)
#define CE_ADM_ERR_SSP_REQ_SHORT			(0x1ULL << 10)
#define CE_ADM_ERR_SSP_REQ_SIDEBAND			(0x1ULL << 11)
#define CE_ADM_ERR_SSP_REQ_ADDR_ERR			(0x1ULL << 12)
#define CE_ADM_ERR_SSP_REQ_BAD_BE			(0x1ULL << 13)
#define CE_ADM_ERR_PCIE_COMPL_TIMEOUT			(0x1ULL << 14)
#define CE_ADM_ERR_PCIE_UNEXP_COMPL			(0x1ULL << 15)
#define CE_ADM_ERR_PCIE_ERR_COMPL			(0x1ULL << 16)
#define CE_ADM_ERR_DRE_CREDIT_OFLOW			(0x1ULL << 17)
#define CE_ADM_ERR_DRE_SRAM_PE				(0x1ULL << 18)
#define CE_ADM_ERR_SSP_RSP_INVALID			(0x1ULL << 19)
#define CE_ADM_ERR_SSP_RSP_LONG				(0x1ULL << 20)
#define CE_ADM_ERR_SSP_RSP_SHORT			(0x1ULL << 21)
#define CE_ADM_ERR_SSP_RSP_SIDEBAND			(0x1ULL << 22)
#define CE_ADM_ERR_URE_SSP_RSP_UNEXP			(0x1ULL << 23)
#define CE_ADM_ERR_URE_SSP_WR_REQ_TIMEOUT		(0x1ULL << 24)
#define CE_ADM_ERR_URE_SSP_RD_REQ_TIMEOUT		(0x1ULL << 25)
#define CE_ADM_ERR_URE_ATE3240_PAGE_FAULT		(0x1ULL << 26)
#define CE_ADM_ERR_URE_ATE40_PAGE_FAULT			(0x1ULL << 27)
#define CE_ADM_ERR_URE_CREDIT_OFLOW			(0x1ULL << 28)
#define CE_ADM_ERR_URE_SRAM_PE				(0x1ULL << 29)
#define CE_ADM_ERR_ADM_SSP_RSP_UNEXP			(0x1ULL << 30)
#define CE_ADM_ERR_ADM_SSP_REQ_TIMEOUT			(0x1ULL << 31)
#define CE_ADM_ERR_MMR_ACCESS_ERROR			(0x1ULL << 32)
#define CE_ADM_ERR_MMR_ADDR_ERROR			(0x1ULL << 33)
#define CE_ADM_ERR_ADM_CREDIT_OFLOW			(0x1ULL << 34)
#define CE_ADM_ERR_ADM_SRAM_PE				(0x1ULL << 35)
#define CE_ADM_ERR_DTL1_MIN_PDATA_CREDIT_ERR		(0x1ULL << 36)
#define CE_ADM_ERR_DTL1_INF_COMPL_CRED_UPDT_ERR		(0x1ULL << 37)
#define CE_ADM_ERR_DTL1_INF_POSTED_CRED_UPDT_ERR	(0x1ULL << 38)
#define CE_ADM_ERR_DTL1_INF_NPOSTED_CRED_UPDT_ERR	(0x1ULL << 39)
#define CE_ADM_ERR_DTL1_COMP_HD_CRED_MAX_ERR		(0x1ULL << 40)
#define CE_ADM_ERR_DTL1_COMP_D_CRED_MAX_ERR		(0x1ULL << 41)
#define CE_ADM_ERR_DTL1_NPOSTED_HD_CRED_MAX_ERR		(0x1ULL << 42)
#define CE_ADM_ERR_DTL1_NPOSTED_D_CRED_MAX_ERR		(0x1ULL << 43)
#define CE_ADM_ERR_DTL1_POSTED_HD_CRED_MAX_ERR		(0x1ULL << 44)
#define CE_ADM_ERR_DTL1_POSTED_D_CRED_MAX_ERR		(0x1ULL << 45)
#define CE_ADM_ERR_DTL2_MIN_PDATA_CREDIT_ERR		(0x1ULL << 46)
#define CE_ADM_ERR_DTL2_INF_COMPL_CRED_UPDT_ERR		(0x1ULL << 47)
#define CE_ADM_ERR_DTL2_INF_POSTED_CRED_UPDT_ERR	(0x1ULL << 48)
#define CE_ADM_ERR_DTL2_INF_NPOSTED_CRED_UPDT_ERR	(0x1ULL << 49)
#define CE_ADM_ERR_DTL2_COMP_HD_CRED_MAX_ERR		(0x1ULL << 50)
#define CE_ADM_ERR_DTL2_COMP_D_CRED_MAX_ERR		(0x1ULL << 51)
#define CE_ADM_ERR_DTL2_NPOSTED_HD_CRED_MAX_ERR		(0x1ULL << 52)
#define CE_ADM_ERR_DTL2_NPOSTED_D_CRED_MAX_ERR		(0x1ULL << 53)
#define CE_ADM_ERR_DTL2_POSTED_HD_CRED_MAX_ERR		(0x1ULL << 54)
#define CE_ADM_ERR_DTL2_POSTED_D_CRED_MAX_ERR		(0x1ULL << 55)
#define CE_ADM_ERR_PORT1_PCIE_COR_ERR			(0x1ULL << 56)
#define CE_ADM_ERR_PORT1_PCIE_NFAT_ERR			(0x1ULL << 57)
#define CE_ADM_ERR_PORT1_PCIE_FAT_ERR			(0x1ULL << 58)
#define CE_ADM_ERR_PORT2_PCIE_COR_ERR			(0x1ULL << 59)
#define CE_ADM_ERR_PORT2_PCIE_NFAT_ERR			(0x1ULL << 60)
#define CE_ADM_ERR_PORT2_PCIE_FAT_ERR			(0x1ULL << 61)

/* ce_adm_ure_ups_buf_barrier_flush register bit masks and shifts */
#define FLUSH_SEL_PORT1_PIPE0_SHFT	0
#define FLUSH_SEL_PORT1_PIPE1_SHFT	4
#define FLUSH_SEL_PORT1_PIPE2_SHFT	8
#define FLUSH_SEL_PORT1_PIPE3_SHFT	12
#define FLUSH_SEL_PORT2_PIPE0_SHFT	16
#define FLUSH_SEL_PORT2_PIPE1_SHFT	20
#define FLUSH_SEL_PORT2_PIPE2_SHFT	24
#define FLUSH_SEL_PORT2_PIPE3_SHFT	28

/* ce_dre_config1 register bit masks and shifts */
#define CE_DRE_RO_ENABLE		(0x1ULL << 0)
#define CE_DRE_DYN_RO_ENABLE		(0x1ULL << 1)
#define CE_DRE_SUP_CONFIG_COMP_ERROR	(0x1ULL << 2)
#define CE_DRE_SUP_IO_COMP_ERROR	(0x1ULL << 3)
#define CE_DRE_ADDR_MODE_SHFT		4

/* ce_dre_config_req_status register bit masks */
#define CE_DRE_LAST_CONFIG_COMPLETION	(0x7ULL << 0)
#define CE_DRE_DOWNSTREAM_CONFIG_ERROR	(0x1ULL << 3)
#define CE_DRE_CONFIG_COMPLETION_VALID	(0x1ULL << 4)
#define CE_DRE_CONFIG_REQUEST_ACTIVE	(0x1ULL << 5)

/* ce_ure_control register bit masks & shifts */
#define CE_URE_RD_MRG_ENABLE		(0x1ULL << 0)
#define CE_URE_WRT_MRG_ENABLE1		(0x1ULL << 4)
#define CE_URE_WRT_MRG_ENABLE2		(0x1ULL << 5)
#define CE_URE_WRT_MRG_TIMER_SHFT	12
#define CE_URE_WRT_MRG_TIMER_MASK	(0x7FFULL << CE_URE_WRT_MRG_TIMER_SHFT)
#define CE_URE_WRT_MRG_TIMER(x)		(((u64)(x) << \
					  CE_URE_WRT_MRG_TIMER_SHFT) & \
					 CE_URE_WRT_MRG_TIMER_MASK)
#define CE_URE_RSPQ_BYPASS_DISABLE	(0x1ULL << 24)
#define CE_URE_UPS_DAT1_PAR_DISABLE	(0x1ULL << 32)
#define CE_URE_UPS_HDR1_PAR_DISABLE	(0x1ULL << 33)
#define CE_URE_UPS_DAT2_PAR_DISABLE	(0x1ULL << 34)
#define CE_URE_UPS_HDR2_PAR_DISABLE	(0x1ULL << 35)
#define CE_URE_ATE_PAR_DISABLE		(0x1ULL << 36)
#define CE_URE_RCI_PAR_DISABLE		(0x1ULL << 37)
#define CE_URE_RSPQ_PAR_DISABLE		(0x1ULL << 38)
#define CE_URE_DNS_DAT_PAR_DISABLE	(0x1ULL << 39)
#define CE_URE_DNS_HDR_PAR_DISABLE	(0x1ULL << 40)
#define CE_URE_MALFORM_DISABLE		(0x1ULL << 44)
#define CE_URE_UNSUP_DISABLE		(0x1ULL << 45)

/* ce_ure_page_map register bit masks & shifts */
#define CE_URE_ATE3240_ENABLE		(0x1ULL << 0)
#define CE_URE_ATE40_ENABLE 		(0x1ULL << 1)
#define CE_URE_PAGESIZE_SHFT		4
#define CE_URE_PAGESIZE_MASK		(0x7ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_4K_PAGESIZE		(0x0ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_16K_PAGESIZE		(0x1ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_64K_PAGESIZE		(0x2ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_128K_PAGESIZE		(0x3ULL << CE_URE_PAGESIZE_SHFT)
#define CE_URE_256K_PAGESIZE		(0x4ULL << CE_URE_PAGESIZE_SHFT)

/* ce_ure_pipe_sel register bit masks & shifts */
#define PKT_TRAFIC_SHRT			16
#define BUS_SRC_ID_SHFT			8
#define DEV_SRC_ID_SHFT			3
#define FNC_SRC_ID_SHFT			0
#define CE_URE_TC_MASK			(0x07ULL << PKT_TRAFIC_SHRT)
#define CE_URE_BUS_MASK			(0xFFULL << BUS_SRC_ID_SHFT)
#define CE_URE_DEV_MASK			(0x1FULL << DEV_SRC_ID_SHFT)
#define CE_URE_FNC_MASK			(0x07ULL << FNC_SRC_ID_SHFT)
#define CE_URE_PIPE_BUS(b)		(((u64)(b) << BUS_SRC_ID_SHFT) & \
					 CE_URE_BUS_MASK)
#define CE_URE_PIPE_DEV(d)		(((u64)(d) << DEV_SRC_ID_SHFT) & \
					 CE_URE_DEV_MASK)
#define CE_URE_PIPE_FNC(f)		(((u64)(f) << FNC_SRC_ID_SHFT) & \
					 CE_URE_FNC_MASK)

#define CE_URE_SEL1_SHFT		0
#define CE_URE_SEL2_SHFT		20
#define CE_URE_SEL3_SHFT		40
#define CE_URE_SEL1_MASK		(0x7FFFFULL << CE_URE_SEL1_SHFT)
#define CE_URE_SEL2_MASK		(0x7FFFFULL << CE_URE_SEL2_SHFT)
#define CE_URE_SEL3_MASK		(0x7FFFFULL << CE_URE_SEL3_SHFT)


/* ce_ure_pipe_mask register bit masks & shifts */
#define CE_URE_MASK1_SHFT		0
#define CE_URE_MASK2_SHFT		20
#define CE_URE_MASK3_SHFT		40
#define CE_URE_MASK1_MASK		(0x7FFFFULL << CE_URE_MASK1_SHFT)
#define CE_URE_MASK2_MASK		(0x7FFFFULL << CE_URE_MASK2_SHFT)
#define CE_URE_MASK3_MASK		(0x7FFFFULL << CE_URE_MASK3_SHFT)


/* ce_ure_pcie_control1 register bit masks & shifts */
#define CE_URE_SI			(0x1ULL << 0)
#define CE_URE_ELAL_SHFT		4
#define CE_URE_ELAL_MASK		(0x7ULL << CE_URE_ELAL_SHFT)
#define CE_URE_ELAL_SET(n)		(((u64)(n) << CE_URE_ELAL_SHFT) & \
					 CE_URE_ELAL_MASK)
#define CE_URE_ELAL1_SHFT		8
#define CE_URE_ELAL1_MASK		(0x7ULL << CE_URE_ELAL1_SHFT)
#define CE_URE_ELAL1_SET(n)		(((u64)(n) << CE_URE_ELAL1_SHFT) & \
					 CE_URE_ELAL1_MASK)
#define CE_URE_SCC			(0x1ULL << 12)
#define CE_URE_PN1_SHFT			16
#define CE_URE_PN1_MASK			(0xFFULL << CE_URE_PN1_SHFT)
#define CE_URE_PN2_SHFT			24
#define CE_URE_PN2_MASK			(0xFFULL << CE_URE_PN2_SHFT)
#define CE_URE_PN1_SET(n)		(((u64)(n) << CE_URE_PN1_SHFT) & \
					 CE_URE_PN1_MASK)
#define CE_URE_PN2_SET(n)		(((u64)(n) << CE_URE_PN2_SHFT) & \
					 CE_URE_PN2_MASK)

/* ce_ure_pcie_control2 register bit masks & shifts */
#define CE_URE_ABP			(0x1ULL << 0)
#define CE_URE_PCP			(0x1ULL << 1)
#define CE_URE_MSP			(0x1ULL << 2)
#define CE_URE_AIP			(0x1ULL << 3)
#define CE_URE_PIP			(0x1ULL << 4)
#define CE_URE_HPS			(0x1ULL << 5)
#define CE_URE_HPC			(0x1ULL << 6)
#define CE_URE_SPLV_SHFT		7
#define CE_URE_SPLV_MASK		(0xFFULL << CE_URE_SPLV_SHFT)
#define CE_URE_SPLV_SET(n)		(((u64)(n) << CE_URE_SPLV_SHFT) & \
					 CE_URE_SPLV_MASK)
#define CE_URE_SPLS_SHFT		15
#define CE_URE_SPLS_MASK		(0x3ULL << CE_URE_SPLS_SHFT)
#define CE_URE_SPLS_SET(n)		(((u64)(n) << CE_URE_SPLS_SHFT) & \
					 CE_URE_SPLS_MASK)
#define CE_URE_PSN1_SHFT		19
#define CE_URE_PSN1_MASK		(0x1FFFULL << CE_URE_PSN1_SHFT)
#define CE_URE_PSN2_SHFT		32
#define CE_URE_PSN2_MASK		(0x1FFFULL << CE_URE_PSN2_SHFT)
#define CE_URE_PSN1_SET(n)		(((u64)(n) << CE_URE_PSN1_SHFT) & \
					 CE_URE_PSN1_MASK)
#define CE_URE_PSN2_SET(n)		(((u64)(n) << CE_URE_PSN2_SHFT) & \
					 CE_URE_PSN2_MASK)

/*
 * PIO address space ranges for CE
 */

/* Local CE Registers Space */
#define CE_PIO_MMR			0x00000000
#define CE_PIO_MMR_LEN			0x04000000

/* PCI Compatible Config Space */
#define CE_PIO_CONFIG_SPACE		0x04000000
#define CE_PIO_CONFIG_SPACE_LEN		0x04000000

/* PCI I/O Space Alias */
#define CE_PIO_IO_SPACE_ALIAS		0x08000000
#define CE_PIO_IO_SPACE_ALIAS_LEN	0x08000000

/* PCI Enhanced Config Space */
#define CE_PIO_E_CONFIG_SPACE		0x10000000
#define CE_PIO_E_CONFIG_SPACE_LEN	0x10000000

/* PCI I/O Space */
#define CE_PIO_IO_SPACE			0x100000000
#define CE_PIO_IO_SPACE_LEN		0x100000000

/* PCI MEM Space */
#define CE_PIO_MEM_SPACE		0x200000000
#define CE_PIO_MEM_SPACE_LEN		TIO_HWIN_SIZE


/*
 * CE PCI Enhanced Config Space shifts & masks
 */
#define CE_E_CONFIG_BUS_SHFT		20
#define CE_E_CONFIG_BUS_MASK		(0xFF << CE_E_CONFIG_BUS_SHFT)
#define CE_E_CONFIG_DEVICE_SHFT		15
#define CE_E_CONFIG_DEVICE_MASK		(0x1F << CE_E_CONFIG_DEVICE_SHFT)
#define CE_E_CONFIG_FUNC_SHFT		12
#define CE_E_CONFIG_FUNC_MASK		(0x7  << CE_E_CONFIG_FUNC_SHFT)

#endif /* __ASM_IA64_SN_TIOCE_H__ */