ipath_registers.h

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/* kr_extstatus bits */
#define INFINIPATH_EXTS_SERDESPLLLOCK 0x1
#define INFINIPATH_EXTS_GPIOIN_MASK 0xFFFFULL
#define INFINIPATH_EXTS_GPIOIN_SHIFT 48

/* kr_extctrl bits */
#define INFINIPATH_EXTC_GPIOINVERT_MASK 0xFFFFULL
#define INFINIPATH_EXTC_GPIOINVERT_SHIFT 32
#define INFINIPATH_EXTC_GPIOOE_MASK 0xFFFFULL
#define INFINIPATH_EXTC_GPIOOE_SHIFT 48
#define INFINIPATH_EXTC_SERDESENABLE         0x80000000ULL
#define INFINIPATH_EXTC_SERDESCONNECT        0x40000000ULL
#define INFINIPATH_EXTC_SERDESENTRUNKING     0x20000000ULL
#define INFINIPATH_EXTC_SERDESDISRXFIFO      0x10000000ULL
#define INFINIPATH_EXTC_SERDESENPLPBK1       0x08000000ULL
#define INFINIPATH_EXTC_SERDESENPLPBK2       0x04000000ULL
#define INFINIPATH_EXTC_SERDESENENCDEC       0x02000000ULL
#define INFINIPATH_EXTC_LED1SECPORT_ON       0x00000020ULL
#define INFINIPATH_EXTC_LED2SECPORT_ON       0x00000010ULL
#define INFINIPATH_EXTC_LED1PRIPORT_ON       0x00000008ULL
#define INFINIPATH_EXTC_LED2PRIPORT_ON       0x00000004ULL
#define INFINIPATH_EXTC_LEDGBLOK_ON          0x00000002ULL
#define INFINIPATH_EXTC_LEDGBLERR_OFF        0x00000001ULL

/* kr_mdio bits */
#define INFINIPATH_MDIO_CLKDIV_MASK 0x7FULL
#define INFINIPATH_MDIO_CLKDIV_SHIFT 32
#define INFINIPATH_MDIO_COMMAND_MASK 0x7ULL
#define INFINIPATH_MDIO_COMMAND_SHIFT 26
#define INFINIPATH_MDIO_DEVADDR_MASK 0x1FULL
#define INFINIPATH_MDIO_DEVADDR_SHIFT 21
#define INFINIPATH_MDIO_REGADDR_MASK 0x1FULL
#define INFINIPATH_MDIO_REGADDR_SHIFT 16
#define INFINIPATH_MDIO_DATA_MASK 0xFFFFULL
#define INFINIPATH_MDIO_DATA_SHIFT 0
#define INFINIPATH_MDIO_CMDVALID    0x0000000040000000ULL
#define INFINIPATH_MDIO_RDDATAVALID 0x0000000080000000ULL

/* kr_partitionkey bits */
#define INFINIPATH_PKEY_SIZE 16
#define INFINIPATH_PKEY_MASK 0xFFFF
#define INFINIPATH_PKEY_DEFAULT_PKEY 0xFFFF

/* kr_serdesconfig0 bits */
#define INFINIPATH_SERDC0_RESET_MASK  0xfULL	/* overal reset bits */
#define INFINIPATH_SERDC0_RESET_PLL   0x10000000ULL	/* pll reset */
/* tx idle enables (per lane) */
#define INFINIPATH_SERDC0_TXIDLE      0xF000ULL
/* rx detect enables (per lane) */
#define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
/* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
#define INFINIPATH_SERDC0_L1PWR_DN	 0xF0ULL

/* kr_xgxsconfig bits */
#define INFINIPATH_XGXS_RESET          0x7ULL
#define INFINIPATH_XGXS_MDIOADDR_MASK  0xfULL
#define INFINIPATH_XGXS_MDIOADDR_SHIFT 4

#define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL	/* 40 bits valid */

/* TID entries (memory), HT400-only */
#define INFINIPATH_RT_VALID 0x8000000000000000ULL
#define INFINIPATH_RT_ADDR_SHIFT 0
#define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF
#define INFINIPATH_RT_BUFSIZE_SHIFT 48

/*
 * IPATH_PIO_MAXIBHDR is the max IB header size allowed for in our
 * PIO send buffers.  This is well beyond anything currently
 * defined in the InfiniBand spec.
 */
#define IPATH_PIO_MAXIBHDR 128

typedef u64 ipath_err_t;

/* mask of defined bits for various registers */
extern u64 infinipath_i_bitsextant;
extern ipath_err_t infinipath_e_bitsextant, infinipath_hwe_bitsextant;

/* masks that are different in various chips, or only exist in some chips */
extern u32 infinipath_i_rcvavail_mask, infinipath_i_rcvurg_mask;

/*
 * register bits for selecting i2c direction and values, used for I2C serial
 * flash
 */
extern u16 ipath_gpio_sda_num, ipath_gpio_scl_num;
extern u64 ipath_gpio_sda, ipath_gpio_scl;

/*
 * These are the infinipath general register numbers (not offsets).
 * The kernel registers are used directly, those beyond the kernel
 * registers are calculated from one of the base registers.  The use of
 * an integer type doesn't allow type-checking as thorough as, say,
 * an enum but allows for better hiding of chip differences.
 */
typedef const u16 ipath_kreg,	/* infinipath general registers */
 ipath_creg,			/* infinipath counter registers */
 ipath_sreg;			/* kernel-only, infinipath send registers */

/*
 * These are the chip registers common to all infinipath chips, and
 * used both by the kernel and the diagnostics or other user code.
 * They are all implemented such that 64 bit accesses work.
 * Some implement no more than 32 bits.  Because 64 bit reads
 * require 2 HT cmds on opteron, we access those with 32 bit
 * reads for efficiency (they are written as 64 bits, since
 * the extra 32 bits are nearly free on writes, and it slightly reduces
 * complexity).  The rest are all accessed as 64 bits.
 */
struct ipath_kregs {
	/* These are the 32 bit group */
	ipath_kreg kr_control;
	ipath_kreg kr_counterregbase;
	ipath_kreg kr_intmask;
	ipath_kreg kr_intstatus;
	ipath_kreg kr_pagealign;
	ipath_kreg kr_portcnt;
	ipath_kreg kr_rcvtidbase;
	ipath_kreg kr_rcvtidcnt;
	ipath_kreg kr_rcvegrbase;
	ipath_kreg kr_rcvegrcnt;
	ipath_kreg kr_scratch;
	ipath_kreg kr_sendctrl;
	ipath_kreg kr_sendpiobufbase;
	ipath_kreg kr_sendpiobufcnt;
	ipath_kreg kr_sendpiosize;
	ipath_kreg kr_sendregbase;
	ipath_kreg kr_userregbase;
	/* These are the 64 bit group */
	ipath_kreg kr_debugport;
	ipath_kreg kr_debugportselect;
	ipath_kreg kr_errorclear;
	ipath_kreg kr_errormask;
	ipath_kreg kr_errorstatus;
	ipath_kreg kr_extctrl;
	ipath_kreg kr_extstatus;
	ipath_kreg kr_gpio_clear;
	ipath_kreg kr_gpio_mask;
	ipath_kreg kr_gpio_out;
	ipath_kreg kr_gpio_status;
	ipath_kreg kr_hwdiagctrl;
	ipath_kreg kr_hwerrclear;
	ipath_kreg kr_hwerrmask;
	ipath_kreg kr_hwerrstatus;
	ipath_kreg kr_ibcctrl;
	ipath_kreg kr_ibcstatus;
	ipath_kreg kr_intblocked;
	ipath_kreg kr_intclear;
	ipath_kreg kr_interruptconfig;
	ipath_kreg kr_mdio;
	ipath_kreg kr_partitionkey;
	ipath_kreg kr_rcvbthqp;
	ipath_kreg kr_rcvbufbase;
	ipath_kreg kr_rcvbufsize;
	ipath_kreg kr_rcvctrl;
	ipath_kreg kr_rcvhdrcnt;
	ipath_kreg kr_rcvhdrentsize;
	ipath_kreg kr_rcvhdrsize;
	ipath_kreg kr_rcvintmembase;
	ipath_kreg kr_rcvintmemsize;
	ipath_kreg kr_revision;
	ipath_kreg kr_sendbuffererror;
	ipath_kreg kr_sendpioavailaddr;
	ipath_kreg kr_serdesconfig0;
	ipath_kreg kr_serdesconfig1;
	ipath_kreg kr_serdesstatus;
	ipath_kreg kr_txintmembase;
	ipath_kreg kr_txintmemsize;
	ipath_kreg kr_xgxsconfig;
	ipath_kreg kr_ibpllcfg;
	/* use these two (and the following N ports) only with
	 * ipath_k*_kreg64_port(); not *kreg64() */
	ipath_kreg kr_rcvhdraddr;
	ipath_kreg kr_rcvhdrtailaddr;

	/* remaining registers are not present on all types of infinipath
	   chips  */
	ipath_kreg kr_rcvpktledcnt;
	ipath_kreg kr_pcierbuftestreg0;
	ipath_kreg kr_pcierbuftestreg1;
	ipath_kreg kr_pcieq0serdesconfig0;
	ipath_kreg kr_pcieq0serdesconfig1;
	ipath_kreg kr_pcieq0serdesstatus;
	ipath_kreg kr_pcieq1serdesconfig0;
	ipath_kreg kr_pcieq1serdesconfig1;
	ipath_kreg kr_pcieq1serdesstatus;
};

struct ipath_cregs {
	ipath_creg cr_badformatcnt;
	ipath_creg cr_erricrccnt;
	ipath_creg cr_errlinkcnt;
	ipath_creg cr_errlpcrccnt;
	ipath_creg cr_errpkey;
	ipath_creg cr_errrcvflowctrlcnt;
	ipath_creg cr_err_rlencnt;
	ipath_creg cr_errslencnt;
	ipath_creg cr_errtidfull;
	ipath_creg cr_errtidvalid;
	ipath_creg cr_errvcrccnt;
	ipath_creg cr_ibstatuschange;
	ipath_creg cr_intcnt;
	ipath_creg cr_invalidrlencnt;
	ipath_creg cr_invalidslencnt;
	ipath_creg cr_lbflowstallcnt;
	ipath_creg cr_iblinkdowncnt;
	ipath_creg cr_iblinkerrrecovcnt;
	ipath_creg cr_ibsymbolerrcnt;
	ipath_creg cr_pktrcvcnt;
	ipath_creg cr_pktrcvflowctrlcnt;
	ipath_creg cr_pktsendcnt;
	ipath_creg cr_pktsendflowcnt;
	ipath_creg cr_portovflcnt;
	ipath_creg cr_rcvebpcnt;
	ipath_creg cr_rcvovflcnt;
	ipath_creg cr_rxdroppktcnt;
	ipath_creg cr_senddropped;
	ipath_creg cr_sendstallcnt;
	ipath_creg cr_sendunderruncnt;
	ipath_creg cr_unsupvlcnt;
	ipath_creg cr_wordrcvcnt;
	ipath_creg cr_wordsendcnt;
};

#endif				/* _IPATH_REGISTERS_H */