shpchp_hpc.c

LINUX 2.6.17.4的源码

	case PCI_SPEED_133MHz_PCIX_533:
		cmd = SETB_PCIX_133MHZ_533;
		break;
	default:
		return -EINVAL;
	}

	retval = shpc_write_cmd(slot, 0, cmd);
	if (retval)
		err("%s: Write command failed!\n", __FUNCTION__);

	DBG_LEAVE_ROUTINE
	return retval;
}

static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
{
	struct controller *ctrl = NULL;
	struct php_ctlr_state_s *php_ctlr;
	u8 schedule_flag = 0;
	u8 temp_byte;
	u32 temp_dword, intr_loc, intr_loc2;
	int hp_slot;

	if (!dev_id)
		return IRQ_NONE;

	if (!shpchp_poll_mode) { 
		ctrl = (struct controller *)dev_id;
		php_ctlr = ctrl->hpc_ctlr_handle;
	} else { 
		php_ctlr = (struct php_ctlr_state_s *) dev_id;
		ctrl = (struct controller *)php_ctlr->callback_instance_id;
	}

	if (!ctrl)
		return IRQ_NONE;
	
	if (!php_ctlr || !php_ctlr->creg)
		return IRQ_NONE;

	/* Check to see if it was our interrupt */
	intr_loc = readl(php_ctlr->creg + INTR_LOC);  

	if (!intr_loc)
		return IRQ_NONE;
	dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc); 

	if(!shpchp_poll_mode) {
		/* Mask Global Interrupt Mask - see implementation note on p. 139 */
		/* of SHPC spec rev 1.0*/
		temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
		temp_dword |= 0x00000001;
		writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);

		intr_loc2 = readl(php_ctlr->creg + INTR_LOC);  
		dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 
	}

	if (intr_loc & 0x0001) {
		/* 
		 * Command Complete Interrupt Pending 
		 * RO only - clear by writing 1 to the Command Completion
		 * Detect bit in Controller SERR-INT register
		 */
		temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
		temp_dword &= 0xfffdffff;
		writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
		ctrl->cmd_busy = 0;
		wake_up_interruptible(&ctrl->queue);
	}

	if ((intr_loc = (intr_loc >> 1)) == 0)
		goto out;

	for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) { 
	/* To find out which slot has interrupt pending */
		if ((intr_loc >> hp_slot) & 0x01) {
			temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
			dbg("%s: Slot %x with intr, slot register = %x\n",
				__FUNCTION__, hp_slot, temp_dword);
			temp_byte = (temp_dword >> 16) & 0xFF;
			if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
				schedule_flag += php_ctlr->switch_change_callback(
					hp_slot, php_ctlr->callback_instance_id);
			if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
				schedule_flag += php_ctlr->attention_button_callback(
					hp_slot, php_ctlr->callback_instance_id);
			if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
				schedule_flag += php_ctlr->presence_change_callback(
					hp_slot , php_ctlr->callback_instance_id);
			if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
				schedule_flag += php_ctlr->power_fault_callback(
					hp_slot, php_ctlr->callback_instance_id);
			
			/* Clear all slot events */
			temp_dword = 0xe01f3fff;
			writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));

			intr_loc2 = readl(php_ctlr->creg + INTR_LOC);  
			dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2); 
		}
	}
 out:
	if (!shpchp_poll_mode) {
		/* Unmask Global Interrupt Mask */
		temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
		temp_dword &= 0xfffffffe;
		writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
	}
	
	return IRQ_HANDLED;
}

static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
{
	int retval = 0;
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
	u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
	u32 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
	u32 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);

	DBG_ENTER_ROUTINE 

	if (pi == 2) {
		if (slot_avail2 & SLOT_133MHZ_PCIX_533)
			bus_speed = PCI_SPEED_133MHz_PCIX_533;
		else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
			bus_speed = PCI_SPEED_100MHz_PCIX_533;
		else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
			bus_speed = PCI_SPEED_66MHz_PCIX_533;
		else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
			bus_speed = PCI_SPEED_133MHz_PCIX_266;
		else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
			bus_speed = PCI_SPEED_100MHz_PCIX_266;
		else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
			bus_speed = PCI_SPEED_66MHz_PCIX_266;
	}

	if (bus_speed == PCI_SPEED_UNKNOWN) {
		if (slot_avail1 & SLOT_133MHZ_PCIX)
			bus_speed = PCI_SPEED_133MHz_PCIX;
		else if (slot_avail1 & SLOT_100MHZ_PCIX)
			bus_speed = PCI_SPEED_100MHz_PCIX;
		else if (slot_avail1 & SLOT_66MHZ_PCIX)
			bus_speed = PCI_SPEED_66MHz_PCIX;
		else if (slot_avail2 & SLOT_66MHZ)
			bus_speed = PCI_SPEED_66MHz;
		else if (slot_avail1 & SLOT_33MHZ)
			bus_speed = PCI_SPEED_33MHz;
		else
			retval = -ENODEV;
	}

	*value = bus_speed;
	dbg("Max bus speed = %d\n", bus_speed);
	DBG_LEAVE_ROUTINE 
	return retval;
}

static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
{
	int retval = 0;
	struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
	enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
	u16 sec_bus_reg = readw(php_ctlr->creg + SEC_BUS_CONFIG);
	u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
	u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);

	DBG_ENTER_ROUTINE 

	if ((pi == 1) && (speed_mode > 4)) {
		*value = PCI_SPEED_UNKNOWN;
		return -ENODEV;
	}

	switch (speed_mode) {
	case 0x0:
		*value = PCI_SPEED_33MHz;
		break;
	case 0x1:
		*value = PCI_SPEED_66MHz;
		break;
	case 0x2:
		*value = PCI_SPEED_66MHz_PCIX;
		break;
	case 0x3:
		*value = PCI_SPEED_100MHz_PCIX;
		break;
	case 0x4:
		*value = PCI_SPEED_133MHz_PCIX;
		break;
	case 0x5:
		*value = PCI_SPEED_66MHz_PCIX_ECC;
		break;
	case 0x6:
		*value = PCI_SPEED_100MHz_PCIX_ECC;
		break;
	case 0x7:
		*value = PCI_SPEED_133MHz_PCIX_ECC;
		break;
	case 0x8:
		*value = PCI_SPEED_66MHz_PCIX_266;
		break;
	case 0x9:
		*value = PCI_SPEED_100MHz_PCIX_266;
		break;
	case 0xa:
		*value = PCI_SPEED_133MHz_PCIX_266;
		break;
	case 0xb:
		*value = PCI_SPEED_66MHz_PCIX_533;
		break;
	case 0xc:
		*value = PCI_SPEED_100MHz_PCIX_533;
		break;
	case 0xd:
		*value = PCI_SPEED_133MHz_PCIX_533;
		break;
	default:
		*value = PCI_SPEED_UNKNOWN;
		retval = -ENODEV;
		break;
	}

	dbg("Current bus speed = %d\n", bus_speed);
	DBG_LEAVE_ROUTINE 
	return retval;
}

static struct hpc_ops shpchp_hpc_ops = {
	.power_on_slot			= hpc_power_on_slot,
	.slot_enable			= hpc_slot_enable,
	.slot_disable			= hpc_slot_disable,
	.set_bus_speed_mode		= hpc_set_bus_speed_mode,	  
	.set_attention_status	= hpc_set_attention_status,
	.get_power_status		= hpc_get_power_status,
	.get_attention_status	= hpc_get_attention_status,
	.get_latch_status		= hpc_get_latch_status,
	.get_adapter_status		= hpc_get_adapter_status,

	.get_max_bus_speed		= hpc_get_max_bus_speed,
	.get_cur_bus_speed		= hpc_get_cur_bus_speed,
	.get_adapter_speed		= hpc_get_adapter_speed,
	.get_mode1_ECC_cap		= hpc_get_mode1_ECC_cap,
	.get_prog_int			= hpc_get_prog_int,

	.query_power_fault		= hpc_query_power_fault,
	.green_led_on			= hpc_set_green_led_on,
	.green_led_off			= hpc_set_green_led_off,
	.green_led_blink		= hpc_set_green_led_blink,
	
	.release_ctlr			= hpc_release_ctlr,
};

inline static int shpc_indirect_creg_read(struct controller *ctrl, int index,
					  u32 *value)
{
	int rc;
	u32 cap_offset = ctrl->cap_offset;
	struct pci_dev *pdev = ctrl->pci_dev;

	rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
	if (rc)
		return rc;
	return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
}

int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
{
	struct php_ctlr_state_s *php_ctlr, *p;
	void *instance_id = ctrl;
	int rc, num_slots = 0;
	u8 hp_slot;
	static int first = 1;
	u32 shpc_base_offset;
	u32 tempdword, slot_reg;
	u8 i;

	DBG_ENTER_ROUTINE

	ctrl->pci_dev = pdev;  /* pci_dev of the P2P bridge */

	spin_lock_init(&list_lock);
	php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);

	if (!php_ctlr) {	/* allocate controller state data */
		err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
		goto abort;
	}

	php_ctlr->pci_dev = pdev;	/* save pci_dev in context */

	if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
				PCI_DEVICE_ID_AMD_GOLAM_7450)) {
		/* amd shpc driver doesn't use Base Offset; assume 0 */
		ctrl->mmio_base = pci_resource_start(pdev, 0);
		ctrl->mmio_size = pci_resource_len(pdev, 0);
	} else {
		ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
		if (!ctrl->cap_offset) {
			err("%s : cap_offset == 0\n", __FUNCTION__);
			goto abort_free_ctlr;
		}
		dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);

		rc = shpc_indirect_creg_read(ctrl, 0, &shpc_base_offset);
		if (rc) {
			err("%s: cannot read base_offset\n", __FUNCTION__);
			goto abort_free_ctlr;
		}

		rc = shpc_indirect_creg_read(ctrl, 3, &tempdword);
		if (rc) {
			err("%s: cannot read slot config\n", __FUNCTION__);
			goto abort_free_ctlr;
		}
		num_slots = tempdword & SLOT_NUM;
		dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);

		for (i = 0; i < 9 + num_slots; i++) {
			rc = shpc_indirect_creg_read(ctrl, i, &tempdword);
			if (rc) {
				err("%s: cannot read creg (index = %d)\n",
				    __FUNCTION__, i);
				goto abort_free_ctlr;
			}
			dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
					tempdword);
		}

		ctrl->mmio_base =
			pci_resource_start(pdev, 0) + shpc_base_offset;
		ctrl->mmio_size = 0x24 + 0x4 * num_slots;
	}

	if (first) {
		spin_lock_init(&hpc_event_lock);
		first = 0;
	}

	info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor, 
		pdev->subsystem_device);
	
	if (pci_enable_device(pdev))
		goto abort_free_ctlr;

	if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
		err("%s: cannot reserve MMIO region\n", __FUNCTION__);
		goto abort_free_ctlr;
	}

	php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
	if (!php_ctlr->creg) {
		err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
		    ctrl->mmio_size, ctrl->mmio_base);
		release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
		goto abort_free_ctlr;
	}
	dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);

	mutex_init(&ctrl->crit_sect);
	mutex_init(&ctrl->cmd_lock);

	/* Setup wait queue */
	init_waitqueue_head(&ctrl->queue);

	/* Find the IRQ */
	php_ctlr->irq = pdev->irq;
	php_ctlr->attention_button_callback = shpchp_handle_attention_button,
	php_ctlr->switch_change_callback = shpchp_handle_switch_change;
	php_ctlr->presence_change_callback = shpchp_handle_presence_change;
	php_ctlr->power_fault_callback = shpchp_handle_power_fault;
	php_ctlr->callback_instance_id = instance_id;

	/* Return PCI Controller Info */
	php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
	php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
	dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
	dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);

	/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
	tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
	dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
	tempdword = 0x0003000f;   
	writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
	tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
	dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);

	/* Mask the MRL sensor SERR Mask of individual slot in
	 * Slot SERR-INT Mask & clear all the existing event if any
	 */
	for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
		slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
		dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
			hp_slot, slot_reg);
		tempdword = 0xffff3fff;  
		writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
	}
	
	if (shpchp_poll_mode)  {/* Install interrupt polling code */
		/* Install and start the interrupt polling timer */
		init_timer(&php_ctlr->int_poll_timer);
		start_int_poll_timer( php_ctlr, 10 );   /* start with 10 second delay */
	} else {
		/* Installs the interrupt handler */
		rc = pci_enable_msi(pdev);
		if (rc) {
			info("Can't get msi for the hotplug controller\n");
			info("Use INTx for the hotplug controller\n");
		} else
			php_ctlr->irq = pdev->irq;
		
		rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
		dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
		if (rc) {
			err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
			goto abort_free_ctlr;
		}
	}
	dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
			pdev->bus->number, PCI_SLOT(pdev->devfn),
			PCI_FUNC(pdev->devfn), pdev->irq);
	get_hp_hw_control_from_firmware(pdev);

	/*  Add this HPC instance into the HPC list */
	spin_lock(&list_lock);
	if (php_ctlr_list_head == 0) {
		php_ctlr_list_head = php_ctlr;
		p = php_ctlr_list_head;
		p->pnext = NULL;
	} else {
		p = php_ctlr_list_head;

		while (p->pnext)
			p = p->pnext;

		p->pnext = php_ctlr;
	}
	spin_unlock(&list_lock);


	ctlr_seq_num++;
	ctrl->hpc_ctlr_handle = php_ctlr;
	ctrl->hpc_ops = &shpchp_hpc_ops;

	for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
		slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
		dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
			hp_slot, slot_reg);
		tempdword = 0xe01f3fff;  
		writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
	}
	if (!shpchp_poll_mode) {
		/* Unmask all general input interrupts and SERR */
		tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
		tempdword = 0x0000000a;
		writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
		tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
		dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
	}

	DBG_LEAVE_ROUTINE
	return 0;

	/* We end up here for the many possible ways to fail this API.  */
abort_free_ctlr:
	kfree(php_ctlr);
abort:
	DBG_LEAVE_ROUTINE
	return -1;
}