📄 budget-av.c
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else if (srate < 5000000) bclk = 0x89; else if (srate < 15000000) bclk = 0x8f; else if (srate < 45000000) bclk = 0x95; m1 = 0x14; if (srate < 4000000) m1 = 0x10; stv0299_writereg(fe, 0x13, aclk); stv0299_writereg(fe, 0x14, bclk); stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff); stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff); stv0299_writereg(fe, 0x21, (ratio) & 0xf0); stv0299_writereg(fe, 0x0f, 0x80 | m1); return 0;}static int philips_su1278_ty_ci_pll_set(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters *params){ u32 div; u8 buf[4]; struct i2c_msg msg = {.addr = 0x61,.flags = 0,.buf = buf,.len = sizeof(buf) }; if ((params->frequency < 950000) || (params->frequency > 2150000)) return -EINVAL; div = (params->frequency + (125 - 1)) / 125; // round correctly buf[0] = (div >> 8) & 0x7f; buf[1] = div & 0xff; buf[2] = 0x80 | ((div & 0x18000) >> 10) | 4; buf[3] = 0x20; if (params->u.qpsk.symbol_rate < 4000000) buf[3] |= 1; if (params->frequency < 1250000) buf[3] |= 0; else if (params->frequency < 1550000) buf[3] |= 0x40; else if (params->frequency < 2050000) buf[3] |= 0x80; else if (params->frequency < 2150000) buf[3] |= 0xC0; if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO; return 0;}#define MIN2(a,b) ((a) < (b) ? (a) : (b))#define MIN3(a,b,c) MIN2(MIN2(a,b),c)static int philips_su1278sh2_tua6100_pll_set(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dvb_frontend_parameters *params){ u8 reg0 [2] = { 0x00, 0x00 }; u8 reg1 [4] = { 0x01, 0x00, 0x00, 0x00 }; u8 reg2 [3] = { 0x02, 0x00, 0x00 }; int _fband; int first_ZF; int R, A, N, P, M; struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = NULL,.len = 0 }; int freq = params->frequency; first_ZF = (freq) / 1000; if (abs(MIN2(abs(first_ZF-1190),abs(first_ZF-1790))) < abs(MIN3(abs(first_ZF-1202),abs(first_ZF-1542),abs(first_ZF-1890)))) _fband = 2; else _fband = 3; if (_fband == 2) { if (((first_ZF >= 950) && (first_ZF < 1350)) || ((first_ZF >= 1430) && (first_ZF < 1950))) reg0[1] = 0x07; else if (((first_ZF >= 1350) && (first_ZF < 1430)) || ((first_ZF >= 1950) && (first_ZF < 2150))) reg0[1] = 0x0B; } if(_fband == 3) { if (((first_ZF >= 950) && (first_ZF < 1350)) || ((first_ZF >= 1455) && (first_ZF < 1950))) reg0[1] = 0x07; else if (((first_ZF >= 1350) && (first_ZF < 1420)) || ((first_ZF >= 1950) && (first_ZF < 2150))) reg0[1] = 0x0B; else if ((first_ZF >= 1420) && (first_ZF < 1455)) reg0[1] = 0x0F; } if (first_ZF > 1525) reg1[1] |= 0x80; else reg1[1] &= 0x7F; if (_fband == 2) { if (first_ZF > 1430) { /* 1430MHZ */ reg1[1] &= 0xCF; /* N2 */ reg2[1] &= 0xCF; /* R2 */ reg2[1] |= 0x10; } else { reg1[1] &= 0xCF; /* N2 */ reg1[1] |= 0x20; reg2[1] &= 0xCF; /* R2 */ reg2[1] |= 0x10; } } if (_fband == 3) { if ((first_ZF >= 1455) && (first_ZF < 1630)) { reg1[1] &= 0xCF; /* N2 */ reg1[1] |= 0x20; reg2[1] &= 0xCF; /* R2 */ } else { if (first_ZF < 1455) { reg1[1] &= 0xCF; /* N2 */ reg1[1] |= 0x20; reg2[1] &= 0xCF; /* R2 */ reg2[1] |= 0x10; } else { if (first_ZF >= 1630) { reg1[1] &= 0xCF; /* N2 */ reg2[1] &= 0xCF; /* R2 */ reg2[1] |= 0x10; } } } } /* set ports, enable P0 for symbol rates > 4Ms/s */ if (params->u.qpsk.symbol_rate >= 4000000) reg1[1] |= 0x0c; else reg1[1] |= 0x04; reg2[1] |= 0x0c; R = 64; A = 64; P = 64; //32 M = (freq * R) / 4; /* in Mhz */ N = (M - A * 1000) / (P * 1000); reg1[1] |= (N >> 9) & 0x03; reg1[2] = (N >> 1) & 0xff; reg1[3] = (N << 7) & 0x80; reg2[1] |= (R >> 8) & 0x03; reg2[2] = R & 0xFF; /* R */ reg1[3] |= A & 0x7f; /* A */ if (P == 64) reg1[1] |= 0x40; /* Prescaler 64/65 */ reg0[1] |= 0x03; /* already enabled - do not reenable i2c repeater or TX fails */ msg.buf = reg0; msg.len = sizeof(reg0); if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO; stv0299_enable_plli2c(fe); msg.buf = reg1; msg.len = sizeof(reg1); if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO; stv0299_enable_plli2c(fe); msg.buf = reg2; msg.len = sizeof(reg2); if (i2c_transfer(i2c, &msg, 1) != 1) return -EIO; return 0;}static u8 typhoon_cinergy1200s_inittab[] = { 0x01, 0x15, 0x02, 0x30, 0x03, 0x00, 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ 0x06, 0x40, /* DAC not used, set to high impendance mode */ 0x07, 0x00, /* DAC LSB */ 0x08, 0x40, /* DiSEqC off */ 0x09, 0x00, /* FIFO */ 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */ 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */ 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */ 0x10, 0x3f, // AGC2 0x3d 0x11, 0x84, 0x12, 0xb9, 0x15, 0xc9, // lock detector threshold 0x16, 0x00, 0x17, 0x00, 0x18, 0x00, 0x19, 0x00, 0x1a, 0x00, 0x1f, 0x50, 0x20, 0x00, 0x21, 0x00, 0x22, 0x00, 0x23, 0x00, 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0 0x29, 0x1e, // 1/2 threshold 0x2a, 0x14, // 2/3 threshold 0x2b, 0x0f, // 3/4 threshold 0x2c, 0x09, // 5/6 threshold 0x2d, 0x05, // 7/8 threshold 0x2e, 0x01, 0x31, 0x1f, // test all FECs 0x32, 0x19, // viterbi and synchro search 0x33, 0xfc, // rs control 0x34, 0x93, // error control 0x0f, 0x92, 0xff, 0xff};static struct stv0299_config typhoon_config = { .demod_address = 0x68, .inittab = typhoon_cinergy1200s_inittab, .mclk = 88000000UL, .invert = 0, .skip_reinit = 0, .lock_output = STV0229_LOCKOUTPUT_1, .volt13_op0_op1 = STV0299_VOLT13_OP0, .min_delay_ms = 100, .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, .pll_set = philips_su1278_ty_ci_pll_set,};static struct stv0299_config cinergy_1200s_config = { .demod_address = 0x68, .inittab = typhoon_cinergy1200s_inittab, .mclk = 88000000UL, .invert = 0, .skip_reinit = 0, .lock_output = STV0229_LOCKOUTPUT_0, .volt13_op0_op1 = STV0299_VOLT13_OP0, .min_delay_ms = 100, .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, .pll_set = philips_su1278_ty_ci_pll_set,};static struct stv0299_config cinergy_1200s_1894_0010_config = { .demod_address = 0x68, .inittab = typhoon_cinergy1200s_inittab, .mclk = 88000000UL, .invert = 1, .skip_reinit = 0, .lock_output = STV0229_LOCKOUTPUT_1, .volt13_op0_op1 = STV0299_VOLT13_OP0, .min_delay_ms = 100, .set_symbol_rate = philips_su1278_ty_ci_set_symbol_rate, .pll_set = philips_su1278sh2_tua6100_pll_set,};static int philips_cu1216_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params){ struct budget *budget = (struct budget *) fe->dvb->priv; u8 buf[4]; struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };#define TUNER_MUL 62500 u32 div = (params->frequency + 36125000 + TUNER_MUL / 2) / TUNER_MUL; buf[0] = (div >> 8) & 0x7f; buf[1] = div & 0xff; buf[2] = 0x86; buf[3] = (params->frequency < 150000000 ? 0x01 : params->frequency < 445000000 ? 0x02 : 0x04); if (i2c_transfer(&budget->i2c_adap, &msg, 1) != 1) return -EIO; return 0;}static struct tda10021_config philips_cu1216_config = { .demod_address = 0x0c, .pll_set = philips_cu1216_pll_set,};static int philips_tu1216_pll_init(struct dvb_frontend *fe){ struct budget *budget = (struct budget *) fe->dvb->priv; static u8 tu1216_init[] = { 0x0b, 0xf5, 0x85, 0xab }; struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tu1216_init,.len = sizeof(tu1216_init) }; // setup PLL configuration if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1) return -EIO; msleep(1); return 0;}static int philips_tu1216_pll_set(struct dvb_frontend *fe, struct dvb_frontend_parameters *params){ struct budget *budget = (struct budget *) fe->dvb->priv; u8 tuner_buf[4]; struct i2c_msg tuner_msg = {.addr = 0x60,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) }; int tuner_frequency = 0; u8 band, cp, filter; // determine charge pump tuner_frequency = params->frequency + 36166000; if (tuner_frequency < 87000000) return -EINVAL; else if (tuner_frequency < 130000000) cp = 3; else if (tuner_frequency < 160000000) cp = 5; else if (tuner_frequency < 200000000) cp = 6; else if (tuner_frequency < 290000000) cp = 3; else if (tuner_frequency < 420000000) cp = 5; else if (tuner_frequency < 480000000) cp = 6; else if (tuner_frequency < 620000000) cp = 3; else if (tuner_frequency < 830000000) cp = 5; else if (tuner_frequency < 895000000) cp = 7; else return -EINVAL; // determine band if (params->frequency < 49000000) return -EINVAL; else if (params->frequency < 161000000) band = 1; else if (params->frequency < 444000000) band = 2; else if (params->frequency < 861000000) band = 4; else return -EINVAL; // setup PLL filter switch (params->u.ofdm.bandwidth) { case BANDWIDTH_6_MHZ: filter = 0; break; case BANDWIDTH_7_MHZ: filter = 0; break; case BANDWIDTH_8_MHZ: filter = 1; break; default: return -EINVAL; } // calculate divisor // ((36166000+((1000000/6)/2)) + Finput)/(1000000/6) tuner_frequency = (((params->frequency / 1000) * 6) + 217496) / 1000; // setup tuner buffer tuner_buf[0] = (tuner_frequency >> 8) & 0x7f; tuner_buf[1] = tuner_frequency & 0xff; tuner_buf[2] = 0xca; tuner_buf[3] = (cp << 5) | (filter << 3) | band; if (i2c_transfer(&budget->i2c_adap, &tuner_msg, 1) != 1) return -EIO; msleep(1); return 0;}static int philips_tu1216_request_firmware(struct dvb_frontend *fe, const struct firmware **fw, char *name){ struct budget *budget = (struct budget *) fe->dvb->priv; return request_firmware(fw, name, &budget->dev->pci->dev);}static struct tda1004x_config philips_tu1216_config = { .demod_address = 0x8, .invert = 1, .invert_oclk = 1, .xtal_freq = TDA10046_XTAL_4M, .agc_config = TDA10046_AGC_DEFAULT, .if_freq = TDA10046_FREQ_3617, .pll_init = philips_tu1216_pll_init, .pll_set = philips_tu1216_pll_set, .pll_sleep = NULL, .request_firmware = philips_tu1216_request_firmware,};static u8 philips_sd1878_inittab[] = { 0x01, 0x15, 0x02, 0x30, 0x03, 0x00, 0x04, 0x7d, 0x05, 0x35, 0x06, 0x40, 0x07, 0x00, 0x08, 0x43, 0x09, 0x02, 0x0C, 0x51, 0x0D, 0x82, 0x0E, 0x23, 0x10, 0x3f, 0x11, 0x84, 0x12, 0xb9, 0x15, 0xc9, 0x16, 0x19, 0x17, 0x8c, 0x18, 0x59, 0x19, 0xf8, 0x1a, 0xfe, 0x1c, 0x7f, 0x1d, 0x00, 0x1e, 0x00, 0x1f, 0x50, 0x20, 0x00, 0x21, 0x00, 0x22, 0x00, 0x23, 0x00, 0x28, 0x00, 0x29, 0x28, 0x2a, 0x14, 0x2b, 0x0f, 0x2c, 0x09, 0x2d, 0x09, 0x31, 0x1f, 0x32, 0x19,
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