📄 pci.c
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/* * pci.c - Low-Level PCI Access in IA-64 * * Derived from bios32.c of i386 tree. * * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P. * David Mosberger-Tang <davidm@hpl.hp.com> * Bjorn Helgaas <bjorn.helgaas@hp.com> * Copyright (C) 2004 Silicon Graphics, Inc. * * Note: Above list of copyright holders is incomplete... */#include <linux/config.h>#include <linux/acpi.h>#include <linux/types.h>#include <linux/kernel.h>#include <linux/pci.h>#include <linux/init.h>#include <linux/ioport.h>#include <linux/slab.h>#include <linux/smp_lock.h>#include <linux/spinlock.h>#include <asm/machvec.h>#include <asm/page.h>#include <asm/system.h>#include <asm/io.h>#include <asm/sal.h>#include <asm/smp.h>#include <asm/irq.h>#include <asm/hw_irq.h>/* * Low-level SAL-based PCI configuration access functions. Note that SAL * calls are already serialized (via sal_lock), so we don't need another * synchronization mechanism here. */#define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \ (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))/* SAL 3.2 adds support for extended config space. */#define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \ (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))static intpci_sal_read (unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 *value){ u64 addr, data = 0; int mode, result; if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) return -EINVAL; if ((seg | reg) <= 255) { addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); mode = 0; } else { addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); mode = 1; } result = ia64_sal_pci_config_read(addr, mode, len, &data); if (result != 0) return -EINVAL; *value = (u32) data; return 0;}static intpci_sal_write (unsigned int seg, unsigned int bus, unsigned int devfn, int reg, int len, u32 value){ u64 addr; int mode, result; if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095)) return -EINVAL; if ((seg | reg) <= 255) { addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg); mode = 0; } else { addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg); mode = 1; } result = ia64_sal_pci_config_write(addr, mode, len, value); if (result != 0) return -EINVAL; return 0;}static struct pci_raw_ops pci_sal_ops = { .read = pci_sal_read, .write = pci_sal_write};struct pci_raw_ops *raw_pci_ops = &pci_sal_ops;static intpci_read (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *value){ return raw_pci_ops->read(pci_domain_nr(bus), bus->number, devfn, where, size, value);}static intpci_write (struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value){ return raw_pci_ops->write(pci_domain_nr(bus), bus->number, devfn, where, size, value);}struct pci_ops pci_root_ops = { .read = pci_read, .write = pci_write,};/* Called by ACPI when it finds a new root bus. */static struct pci_controller * __devinitalloc_pci_controller (int seg){ struct pci_controller *controller; controller = kmalloc(sizeof(*controller), GFP_KERNEL); if (!controller) return NULL; memset(controller, 0, sizeof(*controller)); controller->segment = seg; controller->node = -1; return controller;}struct pci_root_info { struct pci_controller *controller; char *name;};static unsigned intnew_space (u64 phys_base, int sparse){ u64 mmio_base; int i; if (phys_base == 0) return 0; /* legacy I/O port space */ mmio_base = (u64) ioremap(phys_base, 0); for (i = 0; i < num_io_spaces; i++) if (io_space[i].mmio_base == mmio_base && io_space[i].sparse == sparse) return i; if (num_io_spaces == MAX_IO_SPACES) { printk(KERN_ERR "PCI: Too many IO port spaces " "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES); return ~0; } i = num_io_spaces++; io_space[i].mmio_base = mmio_base; io_space[i].sparse = sparse; return i;}static u64 __devinitadd_io_space (struct pci_root_info *info, struct acpi_resource_address64 *addr){ struct resource *resource; char *name; u64 base, min, max, base_port; unsigned int sparse = 0, space_nr, len; resource = kzalloc(sizeof(*resource), GFP_KERNEL); if (!resource) { printk(KERN_ERR "PCI: No memory for %s I/O port space\n", info->name); goto out; } len = strlen(info->name) + 32; name = kzalloc(len, GFP_KERNEL); if (!name) { printk(KERN_ERR "PCI: No memory for %s I/O port space name\n", info->name); goto free_resource; } min = addr->minimum; max = min + addr->address_length - 1; if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION) sparse = 1; space_nr = new_space(addr->translation_offset, sparse); if (space_nr == ~0) goto free_name; base = __pa(io_space[space_nr].mmio_base); base_port = IO_SPACE_BASE(space_nr); snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name, base_port + min, base_port + max); /* * The SDM guarantees the legacy 0-64K space is sparse, but if the * mapping is done by the processor (not the bridge), ACPI may not * mark it as sparse. */ if (space_nr == 0) sparse = 1; resource->name = name; resource->flags = IORESOURCE_MEM; resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min); resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max); insert_resource(&iomem_resource, resource); return base_port;free_name: kfree(name);free_resource: kfree(resource);out: return ~0;}static acpi_status __devinit resource_to_window(struct acpi_resource *resource, struct acpi_resource_address64 *addr){ acpi_status status; /* * We're only interested in _CRS descriptors that are * - address space descriptors for memory or I/O space * - non-zero size * - producers, i.e., the address space is routed downstream, * not consumed by the bridge itself */ status = acpi_resource_to_address64(resource, addr); if (ACPI_SUCCESS(status) && (addr->resource_type == ACPI_MEMORY_RANGE || addr->resource_type == ACPI_IO_RANGE) && addr->address_length && addr->producer_consumer == ACPI_PRODUCER) return AE_OK; return AE_ERROR;}static acpi_status __devinitcount_window (struct acpi_resource *resource, void *data){ unsigned int *windows = (unsigned int *) data; struct acpi_resource_address64 addr; acpi_status status; status = resource_to_window(resource, &addr); if (ACPI_SUCCESS(status)) (*windows)++; return AE_OK;}static __devinit acpi_status add_window(struct acpi_resource *res, void *data){ struct pci_root_info *info = data; struct pci_window *window; struct acpi_resource_address64 addr; acpi_status status; unsigned long flags, offset = 0; struct resource *root; /* Return AE_OK for non-window resources to keep scanning for more */ status = resource_to_window(res, &addr); if (!ACPI_SUCCESS(status)) return AE_OK; if (addr.resource_type == ACPI_MEMORY_RANGE) { flags = IORESOURCE_MEM; root = &iomem_resource; offset = addr.translation_offset; } else if (addr.resource_type == ACPI_IO_RANGE) { flags = IORESOURCE_IO; root = &ioport_resource; offset = add_io_space(info, &addr); if (offset == ~0) return AE_OK; } else return AE_OK; window = &info->controller->window[info->controller->windows++]; window->resource.name = info->name; window->resource.flags = flags; window->resource.start = addr.minimum + offset; window->resource.end = window->resource.start + addr.address_length - 1; window->resource.child = NULL; window->offset = offset; if (insert_resource(root, &window->resource)) { printk(KERN_ERR "alloc 0x%lx-0x%lx from %s for %s failed\n", window->resource.start, window->resource.end, root->name, info->name); } return AE_OK;}static void __devinitpcibios_setup_root_windows(struct pci_bus *bus, struct pci_controller *ctrl){ int i, j; j = 0; for (i = 0; i < ctrl->windows; i++) { struct resource *res = &ctrl->window[i].resource; /* HP's firmware has a hack to work around a Windows bug. * Ignore these tiny memory ranges */ if ((res->flags & IORESOURCE_MEM) && (res->end - res->start < 16)) continue; if (j >= PCI_BUS_NUM_RESOURCES) { printk("Ignoring range [%lx-%lx] (%lx)\n", res->start, res->end, res->flags); continue; } bus->resource[j++] = res; }}struct pci_bus * __devinitpci_acpi_scan_root(struct acpi_device *device, int domain, int bus){ struct pci_root_info info; struct pci_controller *controller; unsigned int windows = 0; struct pci_bus *pbus; char *name; int pxm; controller = alloc_pci_controller(domain); if (!controller) goto out1; controller->acpi_handle = device->handle; pxm = acpi_get_pxm(controller->acpi_handle);#ifdef CONFIG_NUMA if (pxm >= 0) controller->node = pxm_to_nid_map[pxm];#endif acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window, &windows); controller->window = kmalloc_node(sizeof(*controller->window) * windows, GFP_KERNEL, controller->node); if (!controller->window) goto out2; name = kmalloc(16, GFP_KERNEL); if (!name) goto out3; sprintf(name, "PCI Bus %04x:%02x", domain, bus); info.controller = controller; info.name = name; acpi_walk_resources(device->handle, METHOD_NAME__CRS, add_window, &info); pbus = pci_scan_bus_parented(NULL, bus, &pci_root_ops, controller); if (pbus) pcibios_setup_root_windows(pbus, controller); return pbus;out3: kfree(controller->window);out2: kfree(controller);out1: return NULL;}void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res){ struct pci_controller *controller = PCI_CONTROLLER(dev); unsigned long offset = 0; int i; for (i = 0; i < controller->windows; i++) { struct pci_window *window = &controller->window[i]; if (!(window->resource.flags & res->flags)) continue; if (window->resource.start > res->start) continue; if (window->resource.end < res->end) continue; offset = window->offset; break; }
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