ip32-irq.c

LINUX 2.6.17.4的源码

/* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 * CRIME register.
 */

#define MACEISA_AUDIO_INT	(MACEISA_AUDIO_SW_INT |		\
				 MACEISA_AUDIO_SC_INT |		\
				 MACEISA_AUDIO1_DMAT_INT |	\
				 MACEISA_AUDIO1_OF_INT |	\
				 MACEISA_AUDIO2_DMAT_INT |	\
				 MACEISA_AUDIO2_MERR_INT |	\
				 MACEISA_AUDIO3_DMAT_INT |	\
				 MACEISA_AUDIO3_MERR_INT)
#define MACEISA_MISC_INT	(MACEISA_RTC_INT |		\
				 MACEISA_KEYB_INT |		\
				 MACEISA_KEYB_POLL_INT |	\
				 MACEISA_MOUSE_INT |		\
				 MACEISA_MOUSE_POLL_INT |	\
				 MACEISA_TIMER0_INT |		\
				 MACEISA_TIMER1_INT |		\
				 MACEISA_TIMER2_INT)
#define MACEISA_SUPERIO_INT	(MACEISA_PARALLEL_INT |		\
				 MACEISA_PAR_CTXA_INT |		\
				 MACEISA_PAR_CTXB_INT |		\
				 MACEISA_PAR_MERR_INT |		\
				 MACEISA_SERIAL1_INT |		\
				 MACEISA_SERIAL1_TDMAT_INT |	\
				 MACEISA_SERIAL1_TDMAPR_INT |	\
				 MACEISA_SERIAL1_TDMAME_INT |	\
				 MACEISA_SERIAL1_RDMAT_INT |	\
				 MACEISA_SERIAL1_RDMAOR_INT |	\
				 MACEISA_SERIAL2_INT |		\
				 MACEISA_SERIAL2_TDMAT_INT |	\
				 MACEISA_SERIAL2_TDMAPR_INT |	\
				 MACEISA_SERIAL2_TDMAME_INT |	\
				 MACEISA_SERIAL2_RDMAT_INT |	\
				 MACEISA_SERIAL2_RDMAOR_INT)

static unsigned long maceisa_mask;

static void enable_maceisa_irq (unsigned int irq)
{
	unsigned int crime_int = 0;
	unsigned long flags;

	DBG ("maceisa enable: %u\n", irq);

	switch (irq) {
	case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
		crime_int = MACE_AUDIO_INT;
		break;
	case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
		crime_int = MACE_MISC_INT;
		break;
	case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
		crime_int = MACE_SUPERIO_INT;
		break;
	}
	DBG ("crime_int %08x enabled\n", crime_int);
	spin_lock_irqsave(&ip32_irq_lock, flags);
	crime_mask |= crime_int;
	crime->imask = crime_mask;
	maceisa_mask |= 1 << (irq - 33);
	mace->perif.ctrl.imask = maceisa_mask;
	spin_unlock_irqrestore(&ip32_irq_lock, flags);
}

static unsigned int startup_maceisa_irq(unsigned int irq)
{
	enable_maceisa_irq(irq);
	return 0;
}

static void disable_maceisa_irq(unsigned int irq)
{
	unsigned int crime_int = 0;
	unsigned long flags;

	spin_lock_irqsave(&ip32_irq_lock, flags);
	maceisa_mask &= ~(1 << (irq - 33));
        if(!(maceisa_mask & MACEISA_AUDIO_INT))
		crime_int |= MACE_AUDIO_INT;
        if(!(maceisa_mask & MACEISA_MISC_INT))
		crime_int |= MACE_MISC_INT;
        if(!(maceisa_mask & MACEISA_SUPERIO_INT))
		crime_int |= MACE_SUPERIO_INT;
	crime_mask &= ~crime_int;
	crime->imask = crime_mask;
	flush_crime_bus();
	mace->perif.ctrl.imask = maceisa_mask;
	flush_mace_bus();
	spin_unlock_irqrestore(&ip32_irq_lock, flags);
}

static void mask_and_ack_maceisa_irq(unsigned int irq)
{
	unsigned long mace_int, flags;

	switch (irq) {
	case MACEISA_PARALLEL_IRQ:
	case MACEISA_SERIAL1_TDMAPR_IRQ:
	case MACEISA_SERIAL2_TDMAPR_IRQ:
		/* edge triggered */
		spin_lock_irqsave(&ip32_irq_lock, flags);
		mace_int = mace->perif.ctrl.istat;
		mace_int &= ~(1 << (irq - 33));
		mace->perif.ctrl.istat = mace_int;
		spin_unlock_irqrestore(&ip32_irq_lock, flags);
		break;
	}
	disable_maceisa_irq(irq);
}

static void end_maceisa_irq(unsigned irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
		enable_maceisa_irq(irq);
}

#define shutdown_maceisa_irq disable_maceisa_irq

static struct hw_interrupt_type ip32_maceisa_interrupt = {
	.typename = "IP32 MACE ISA",
	.startup = startup_maceisa_irq,
	.shutdown = shutdown_maceisa_irq,
	.enable = enable_maceisa_irq,
	.disable = disable_maceisa_irq,
	.ack = mask_and_ack_maceisa_irq,
	.end = end_maceisa_irq,
};

/* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 * bits 0-3 and 7 in the CRIME register.
 */

static void enable_mace_irq(unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&ip32_irq_lock, flags);
	crime_mask |= 1 << (irq - 1);
	crime->imask = crime_mask;
	spin_unlock_irqrestore(&ip32_irq_lock, flags);
}

static unsigned int startup_mace_irq(unsigned int irq)
{
	enable_mace_irq(irq);
	return 0;
}

static void disable_mace_irq(unsigned int irq)
{
	unsigned long flags;

	spin_lock_irqsave(&ip32_irq_lock, flags);
	crime_mask &= ~(1 << (irq - 1));
	crime->imask = crime_mask;
	flush_crime_bus();
	spin_unlock_irqrestore(&ip32_irq_lock, flags);
}

static void end_mace_irq(unsigned int irq)
{
	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
		enable_mace_irq(irq);
}

#define shutdown_mace_irq disable_mace_irq
#define mask_and_ack_mace_irq disable_mace_irq

static struct hw_interrupt_type ip32_mace_interrupt = {
	.typename = "IP32 MACE",
	.startup = startup_mace_irq,
	.shutdown = shutdown_mace_irq,
	.enable = enable_mace_irq,
	.disable = disable_mace_irq,
	.ack = mask_and_ack_mace_irq,
	.end = end_mace_irq,
};

static void ip32_unknown_interrupt(struct pt_regs *regs)
{
	printk ("Unknown interrupt occurred!\n");
	printk ("cp0_status: %08x\n", read_c0_status());
	printk ("cp0_cause: %08x\n", read_c0_cause());
	printk ("CRIME intr mask: %016lx\n", crime->imask);
	printk ("CRIME intr status: %016lx\n", crime->istat);
	printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
	printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
	printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
	printk ("MACE PCI control register: %08x\n", mace->pci.control);

	printk("Register dump:\n");
	show_regs(regs);

	printk("Please mail this report to [e-mail]\n");
	printk("Spinning...");
	while(1) ;
}

/* CRIME 1.1 appears to deliver all interrupts to this one pin. */
/* change this to loop over all edge-triggered irqs, exception masked out ones */
static void ip32_irq0(struct pt_regs *regs)
{
	uint64_t crime_int;
	int irq = 0;

	crime_int = crime->istat & crime_mask;
	irq = __ffs(crime_int);
	crime_int = 1 << irq;

	if (crime_int & CRIME_MACEISA_INT_MASK) {
		unsigned long mace_int = mace->perif.ctrl.istat;
		irq = __ffs(mace_int & maceisa_mask) + 32;
	}
	irq++;
	DBG("*irq %u*\n", irq);
	do_IRQ(irq, regs);
}

static void ip32_irq1(struct pt_regs *regs)
{
	ip32_unknown_interrupt(regs);
}

static void ip32_irq2(struct pt_regs *regs)
{
	ip32_unknown_interrupt(regs);
}

static void ip32_irq3(struct pt_regs *regs)
{
	ip32_unknown_interrupt(regs);
}

static void ip32_irq4(struct pt_regs *regs)
{
	ip32_unknown_interrupt(regs);
}

static void ip32_irq5(struct pt_regs *regs)
{
	ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs);
}

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	unsigned int pending = read_c0_cause();

	if (likely(pending & IE_IRQ0))
		ip32_irq0(regs);
	else if (unlikely(pending & IE_IRQ1))
		ip32_irq1(regs);
	else if (unlikely(pending & IE_IRQ2))
		ip32_irq2(regs);
	else if (unlikely(pending & IE_IRQ3))
		ip32_irq3(regs);
	else if (unlikely(pending & IE_IRQ4))
		ip32_irq4(regs);
	else if (likely(pending & IE_IRQ5))
		ip32_irq5(regs);
}

void __init arch_init_irq(void)
{
	unsigned int irq;

	/* Install our interrupt handler, then clear and disable all
	 * CRIME and MACE interrupts. */
	crime->imask = 0;
	crime->hard_int = 0;
	crime->soft_int = 0;
	mace->perif.ctrl.istat = 0;
	mace->perif.ctrl.imask = 0;

	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
		hw_irq_controller *controller;

		if (irq == IP32_R4K_TIMER_IRQ)
			controller = &ip32_cpu_interrupt;
		else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
			controller = &ip32_mace_interrupt;
		else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
			controller = &ip32_macepci_interrupt;
		else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
			controller = &ip32_crime_interrupt;
		else
			controller = &ip32_maceisa_interrupt;

		irq_desc[irq].status = IRQ_DISABLED;
		irq_desc[irq].action = 0;
		irq_desc[irq].depth = 0;
		irq_desc[irq].handler = controller;
	}
	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
	change_c0_status(ST0_IM, ALLINTS);
}