irq.c

LINUX 2.6.17.4的源码

				irq_desc[irq_nr].handler = &fall_edge_irq_type;
				break;
			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG1SET);
				au_writel(1<<(irq_nr-32), IC1_CFG0SET);
				irq_desc[irq_nr].handler = &either_edge_irq_type;
				break;
			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
				au_writel(1<<(irq_nr-32), IC1_CFG2SET);
				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG0SET);
				irq_desc[irq_nr].handler = &level_irq_type;
				break;
			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
				au_writel(1<<(irq_nr-32), IC1_CFG2SET);
				au_writel(1<<(irq_nr-32), IC1_CFG1SET);
				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
				irq_desc[irq_nr].handler = &level_irq_type;
				break;
			case INTC_INT_DISABLED: /* 0:0:0 */
				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
				break;
			default: /* disable the interrupt */
				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
				return;
		}
		if (int_req) /* assign to interrupt request 1 */
			au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
		else	     /* assign to interrupt request 0 */
			au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
		au_writel(1<<(irq_nr-32), IC1_SRCSET);
		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
		au_writel(1<<(irq_nr-32), IC1_WAKECLR);
	}
	else {
		switch (type) {
			case INTC_INT_RISE_EDGE: /* 0:0:1 */
				au_writel(1<<irq_nr, IC0_CFG2CLR);
				au_writel(1<<irq_nr, IC0_CFG1CLR);
				au_writel(1<<irq_nr, IC0_CFG0SET);
				irq_desc[irq_nr].handler = &rise_edge_irq_type;
				break;
			case INTC_INT_FALL_EDGE: /* 0:1:0 */
				au_writel(1<<irq_nr, IC0_CFG2CLR);
				au_writel(1<<irq_nr, IC0_CFG1SET);
				au_writel(1<<irq_nr, IC0_CFG0CLR);
				irq_desc[irq_nr].handler = &fall_edge_irq_type;
				break;
			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
				au_writel(1<<irq_nr, IC0_CFG2CLR);
				au_writel(1<<irq_nr, IC0_CFG1SET);
				au_writel(1<<irq_nr, IC0_CFG0SET);
				irq_desc[irq_nr].handler = &either_edge_irq_type;
				break;
			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
				au_writel(1<<irq_nr, IC0_CFG2SET);
				au_writel(1<<irq_nr, IC0_CFG1CLR);
				au_writel(1<<irq_nr, IC0_CFG0SET);
				irq_desc[irq_nr].handler = &level_irq_type;
				break;
			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
				au_writel(1<<irq_nr, IC0_CFG2SET);
				au_writel(1<<irq_nr, IC0_CFG1SET);
				au_writel(1<<irq_nr, IC0_CFG0CLR);
				irq_desc[irq_nr].handler = &level_irq_type;
				break;
			case INTC_INT_DISABLED: /* 0:0:0 */
				au_writel(1<<irq_nr, IC0_CFG0CLR);
				au_writel(1<<irq_nr, IC0_CFG1CLR);
				au_writel(1<<irq_nr, IC0_CFG2CLR);
				break;
			default: /* disable the interrupt */
				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
				au_writel(1<<irq_nr, IC0_CFG0CLR);
				au_writel(1<<irq_nr, IC0_CFG1CLR);
				au_writel(1<<irq_nr, IC0_CFG2CLR);
				return;
		}
		if (int_req) /* assign to interrupt request 1 */
			au_writel(1<<irq_nr, IC0_ASSIGNCLR);
		else	     /* assign to interrupt request 0 */
			au_writel(1<<irq_nr, IC0_ASSIGNSET);
		au_writel(1<<irq_nr, IC0_SRCSET);
		au_writel(1<<irq_nr, IC0_MASKCLR);
		au_writel(1<<irq_nr, IC0_WAKECLR);
	}
	au_sync();
}


void __init arch_init_irq(void)
{
	int i;
	unsigned long cp0_status;
	au1xxx_irq_map_t *imp;
	extern au1xxx_irq_map_t au1xxx_irq_map[];
	extern au1xxx_irq_map_t au1xxx_ic0_map[];
	extern int au1xxx_nr_irqs;
	extern int au1xxx_ic0_nr_irqs;

	cp0_status = read_c0_status();

	/* Initialize interrupt controllers to a safe state.
	*/
	au_writel(0xffffffff, IC0_CFG0CLR);
	au_writel(0xffffffff, IC0_CFG1CLR);
	au_writel(0xffffffff, IC0_CFG2CLR);
	au_writel(0xffffffff, IC0_MASKCLR);
	au_writel(0xffffffff, IC0_ASSIGNSET);
	au_writel(0xffffffff, IC0_WAKECLR);
	au_writel(0xffffffff, IC0_SRCSET);
	au_writel(0xffffffff, IC0_FALLINGCLR);
	au_writel(0xffffffff, IC0_RISINGCLR);
	au_writel(0x00000000, IC0_TESTBIT);

	au_writel(0xffffffff, IC1_CFG0CLR);
	au_writel(0xffffffff, IC1_CFG1CLR);
	au_writel(0xffffffff, IC1_CFG2CLR);
	au_writel(0xffffffff, IC1_MASKCLR);
	au_writel(0xffffffff, IC1_ASSIGNSET);
	au_writel(0xffffffff, IC1_WAKECLR);
	au_writel(0xffffffff, IC1_SRCSET);
	au_writel(0xffffffff, IC1_FALLINGCLR);
	au_writel(0xffffffff, IC1_RISINGCLR);
	au_writel(0x00000000, IC1_TESTBIT);

	/* Initialize IC0, which is fixed per processor.
	*/
	imp = au1xxx_ic0_map;
	for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	/* Now set up the irq mapping for the board.
	*/
	imp = au1xxx_irq_map;
	for (i=0; i<au1xxx_nr_irqs; i++) {
		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
		imp++;
	}

	set_c0_status(ALLINTS);

	/* Board specific IRQ initialization.
	*/
	if (board_init_irq)
		(*board_init_irq)();
}


/*
 * Interrupts are nested. Even if an interrupt handler is registered
 * as "fast", we might get another interrupt before we return from
 * intcX_reqX_irqdispatch().
 */

void intc0_req0_irqdispatch(struct pt_regs *regs)
{
	int irq = 0;
	static unsigned long intc0_req0 = 0;

	intc0_req0 |= au_readl(IC0_REQ0INT);

	if (!intc0_req0) return;
#ifdef AU1000_USB_DEV_REQ_INT
	/*
	 * Because of the tight timing of SETUP token to reply
	 * transactions, the USB devices-side packet complete
	 * interrupt needs the highest priority.
	 */
	if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
		intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
		do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
		return;
	}
#endif
	irq = au_ffs(intc0_req0) - 1;
	intc0_req0 &= ~(1<<irq);
	do_IRQ(irq, regs);
}


void intc0_req1_irqdispatch(struct pt_regs *regs)
{
	int irq = 0;
	static unsigned long intc0_req1 = 0;

	intc0_req1 |= au_readl(IC0_REQ1INT);

	if (!intc0_req1) return;

	irq = au_ffs(intc0_req1) - 1;
	intc0_req1 &= ~(1<<irq);
	do_IRQ(irq, regs);
}


/*
 * Interrupt Controller 1:
 * interrupts 32 - 63
 */
void intc1_req0_irqdispatch(struct pt_regs *regs)
{
	int irq = 0;
	static unsigned long intc1_req0 = 0;

	intc1_req0 |= au_readl(IC1_REQ0INT);

	if (!intc1_req0) return;

	irq = au_ffs(intc1_req0) - 1;
	intc1_req0 &= ~(1<<irq);
	irq += 32;
	do_IRQ(irq, regs);
}


void intc1_req1_irqdispatch(struct pt_regs *regs)
{
	int irq = 0;
	static unsigned long intc1_req1 = 0;

	intc1_req1 |= au_readl(IC1_REQ1INT);

	if (!intc1_req1) return;

	irq = au_ffs(intc1_req1) - 1;
	intc1_req1 &= ~(1<<irq);
	irq += 32;
	do_IRQ(irq, regs);
}

#ifdef CONFIG_PM

/* Save/restore the interrupt controller state.
 * Called from the save/restore core registers as part of the
 * au_sleep function in power.c.....maybe I should just pm_register()
 * them instead?
 */
static uint	sleep_intctl_config0[2];
static uint	sleep_intctl_config1[2];
static uint	sleep_intctl_config2[2];
static uint	sleep_intctl_src[2];
static uint	sleep_intctl_assign[2];
static uint	sleep_intctl_wake[2];
static uint	sleep_intctl_mask[2];

void
save_au1xxx_intctl(void)
{
	sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
	sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
	sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
	sleep_intctl_src[0] = au_readl(IC0_SRCRD);
	sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
	sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
	sleep_intctl_mask[0] = au_readl(IC0_MASKRD);

	sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
	sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
	sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
	sleep_intctl_src[1] = au_readl(IC1_SRCRD);
	sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
	sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
	sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
}

/* For most restore operations, we clear the entire register and
 * then set the bits we found during the save.
 */
void
restore_au1xxx_intctl(void)
{
	au_writel(0xffffffff, IC0_MASKCLR); au_sync();

	au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
	au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
	au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
	au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
	au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
	au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
	au_writel(0xffffffff, IC0_SRCCLR); au_sync();
	au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
	au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
	au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
	au_writel(0xffffffff, IC0_WAKECLR); au_sync();
	au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
	au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
	au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
	au_writel(0x00000000, IC0_TESTBIT); au_sync();

	au_writel(0xffffffff, IC1_MASKCLR); au_sync();

	au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
	au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
	au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
	au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
	au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
	au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
	au_writel(0xffffffff, IC1_SRCCLR); au_sync();
	au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
	au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
	au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
	au_writel(0xffffffff, IC1_WAKECLR); au_sync();
	au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
	au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
	au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
	au_writel(0x00000000, IC1_TESTBIT); au_sync();

	au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();

	au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
}
#endif /* CONFIG_PM */

asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;

	if (pending & CAUSEF_IP7)
		mips_timer_interrupt(regs);
	else if (pending & CAUSEF_IP2)
		intc0_req0_irqdispatch(regs);
	else if (pending & CAUSEF_IP3)
		intc0_req1_irqdispatch(regs);
	else if (pending & CAUSEF_IP4)
		intc1_req0_irqdispatch(regs);
	else if (pending  & CAUSEF_IP5)
		intc1_req1_irqdispatch(regs);
	else
		spurious_interrupt(regs);
}