toshiba_rbtx4927_setup.c

LINUX 2.6.17.4的源码

					       pci_devfn, 0x04, &v08_04);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x09, &v08_09);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x41, &v08_41);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x43, &v08_43);
			early_read_config_byte(hose, busno, busno,
					       pci_devfn, 0x5c, &v08_5c);

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x04 = 0x%02x\n", s, v08_04);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x09 = 0x%02x\n", s, v08_09);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x41 = 0x%02x\n", s, v08_41);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x43 = 0x%02x\n", s, v08_43);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s beg 0x5c = 0x%02x\n", s, v08_5c);

			/* enable ide master/io */
			v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);

			/* enable ide native mode */
			v08_09 |= 0x05;

			/* enable primary ide */
			v08_41 |= 0x80;

			/* enable secondary ide */
			v08_43 |= 0x80;

			/*
			 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
			 *
			 * This line of code is intended to provide the user with a work
			 * around solution to the anomalies cited in SMSC's anomaly sheet
			 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
			 *
			 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
			 */
			v08_5c |= 0x01;

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x04 = 0x%02x\n", s, v08_04);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x09 = 0x%02x\n", s, v08_09);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x41 = 0x%02x\n", s, v08_41);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x43 = 0x%02x\n", s, v08_43);
			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
			     ":%s mid 0x5c = 0x%02x\n", s, v08_5c);

			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x5c, v08_5c);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x04, v08_04);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x09, v08_09);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x41, v08_41);
			early_write_config_byte(hose, busno, busno,
						pci_devfn, 0x43, v08_43);

#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
			{
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x04,
						       &v08_04);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x09,
						       &v08_09);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x41,
						       &v08_41);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x43,
						       &v08_43);
				early_read_config_byte(hose, busno, busno,
						       pci_devfn, 0x5c,
						       &v08_5c);

				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x04 = 0x%02x\n", s, v08_04);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x09 = 0x%02x\n", s, v08_09);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x41 = 0x%02x\n", s, v08_41);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x43 = 0x%02x\n", s, v08_43);
				TOSHIBA_RBTX4927_SETUP_DPRINTK
				    (TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				     ":%s end 0x5c = 0x%02x\n", s, v08_5c);
			}
#endif

			TOSHIBA_RBTX4927_SETUP_DPRINTK
			    (TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
			     s);
		}

	}

	register_pci_controller(&tx4927_controller);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
				       "+\n");

	return 0;
}

arch_initcall(tx4927_pcibios_init);

extern struct resource pci_io_resource;
extern struct resource pci_mem_resource;

void tx4927_pci_setup(void)
{
	static int called = 0;
	extern unsigned int tx4927_get_mem_size(void);

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");

	mips_memory_upper = tx4927_get_mem_size() << 20;
	mips_memory_upper += KSEG0;
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_memory_upper\n",
				       mips_memory_upper);
	mips_pci_io_base = TX4927_PCIIO;
	mips_pci_io_size = TX4927_PCIIO_SIZE;
	mips_pci_mem_base = TX4927_PCIMEM;
	mips_pci_mem_size = TX4927_PCIMEM_SIZE;

	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_io_base\n",
				       mips_pci_io_base);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_io_size\n",
				       mips_pci_io_size);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_mem_base\n",
				       mips_pci_mem_base);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_pci_mem_size\n",
				       mips_pci_mem_size);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_io_resource.start\n",
				       pci_io_resource.start);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_io_resource.end\n",
				       pci_io_resource.end);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_mem_resource.start\n",
				       pci_mem_resource.start);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=pci_mem_resource.end\n",
				       pci_mem_resource.end);
	TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
				       "0x%08lx=mips_io_port_base",
				       mips_io_port_base);
	if (!called) {
		printk
		    ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
		     toshiba_name,
		     (unsigned short) (tx4927_pcicptr->pciid >> 16),
		     (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
		     (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
		     (!(tx4927_ccfgptr->
			ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
		     "Internal");
		called = 1;
	}
	printk("%s PCIC --%s PCICLK:",toshiba_name,
	       (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
	if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
		int pciclk = 0;
		if (mips_machtype == MACH_TOSHIBA_RBTX4937)
			switch ((unsigned long) tx4927_ccfgptr->
				ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
			case TX4937_CCFG_PCIDIVMODE_4:
				pciclk = tx4927_cpu_clock / 4;
				break;
			case TX4937_CCFG_PCIDIVMODE_4_5:
				pciclk = tx4927_cpu_clock * 2 / 9;
				break;
			case TX4937_CCFG_PCIDIVMODE_5:
				pciclk = tx4927_cpu_clock / 5;
				break;
			case TX4937_CCFG_PCIDIVMODE_5_5:
				pciclk = tx4927_cpu_clock * 2 / 11;
				break;
			case TX4937_CCFG_PCIDIVMODE_8:
				pciclk = tx4927_cpu_clock / 8;
				break;
			case TX4937_CCFG_PCIDIVMODE_9:
				pciclk = tx4927_cpu_clock / 9;
				break;
			case TX4937_CCFG_PCIDIVMODE_10:
				pciclk = tx4927_cpu_clock / 10;
				break;
			case TX4937_CCFG_PCIDIVMODE_11:
				pciclk = tx4927_cpu_clock / 11;
				break;
			}

		else
			switch ((unsigned long) tx4927_ccfgptr->
				ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
			case TX4927_CCFG_PCIDIVMODE_2_5:
				pciclk = tx4927_cpu_clock * 2 / 5;
				break;
			case TX4927_CCFG_PCIDIVMODE_3:
				pciclk = tx4927_cpu_clock / 3;
				break;
			case TX4927_CCFG_PCIDIVMODE_5:
				pciclk = tx4927_cpu_clock / 5;
				break;
			case TX4927_CCFG_PCIDIVMODE_6:
				pciclk = tx4927_cpu_clock / 6;
				break;
			}

		printk("Internal(%dMHz)", pciclk / 1000000);
	} else {
		int pciclk = 0;
		int pciclk_setting = *tx4927_pci_clk_ptr;
		switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
		case TX4927_PCI_CLK_33:
			pciclk = 33333333;
			break;
		case TX4927_PCI_CLK_25:
			pciclk = 25000000;
			break;
		case TX4927_PCI_CLK_66:
			pciclk = 66666666;
			break;
		case TX4927_PCI_CLK_50:
			pciclk = 50000000;
			break;
		}
		printk("External(%dMHz)", pciclk / 1000000);
	}
	printk("\n");



	/* GB->PCI mappings */
	tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
	tx4927_pcicptr->g2piogbase = mips_pci_io_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PIOGBASE_ECHG
#else
	    TX4927_PCIC_G2PIOGBASE_BSDIS
#endif
	    ;

	tx4927_pcicptr->g2piopbase = 0;

	tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
	tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_G2PMnGBASE_ECHG
#else
	    TX4927_PCIC_G2PMnGBASE_BSDIS
#endif
	    ;
	tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;

	tx4927_pcicptr->g2pmmask[1] = 0;
	tx4927_pcicptr->g2pmgbase[1] = 0;
	tx4927_pcicptr->g2pmpbase[1] = 0;
	tx4927_pcicptr->g2pmmask[2] = 0;
	tx4927_pcicptr->g2pmgbase[2] = 0;
	tx4927_pcicptr->g2pmpbase[2] = 0;


	/* PCI->GB mappings (I/O 256B) */
	tx4927_pcicptr->p2giopbase = 0;	/* 256B */

	/* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
	tx4927_pcicptr->p2gm0plbase = 0;
	tx4927_pcicptr->p2gm0pubase = 0;
	tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
#ifdef __BIG_ENDIAN
	    TX4927_PCIC_P2GMnGBASE_TECHG
#else
	    TX4927_PCIC_P2GMnGBASE_TBSDIS
#endif
	    ;

	/* PCI->GB mappings (MEM 16MB) -not used */
	tx4927_pcicptr->p2gm1plbase = 0xffffffff;
#ifdef CONFIG_TX4927BUG_WORKAROUND
	/*
	 * TX4927-PCIC-BUG: P2GM1PUBASE must be 0
	 * if P2GM0PUBASE was 0.
	 */
	tx4927_pcicptr->p2gm1pubase = 0;
#else
	tx4927_pcicptr->p2gm1pubase = 0xffffffff;
#endif
	tx4927_pcicptr->p2gmgbase[1] = 0;

	/* PCI->GB mappings (MEM 1MB) -not used */
	tx4927_pcicptr->p2gm2pbase = 0xffffffff;
	tx4927_pcicptr->p2gmgbase[2] = 0;


	/* Enable Initiator Memory 0 Space, I/O Space, Config */
	tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
	tx4927_pcicptr->pciccfg |=
	    TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
	    TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;


	/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
	tx4927_pcicptr->pcicfg1 = 0;

	if (tx4927_pcic_trdyto >= 0) {
		tx4927_pcicptr->g2ptocnt &= ~0xff;
		tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
	}

	/* Clear All Local Bus Status */
	tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
	/* Enable All Local Bus Interrupts */
	tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
	/* Clear All Initiator Status */
	tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
	/* Enable All Initiator Interrupts */
	tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
	/* Clear All PCI Status Error */
	tx4927_pcicptr->pcistatus =
	    (tx4927_pcicptr->pcistatus & 0x0000ffff) |
	    (TX4927_PCIC_PCISTATUS_ALL << 16);
	/* Enable All PCI Status Error Interrupts */
	tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;

	/* PCIC Int => IRC IRQ16 */
	tx4927_pcicptr->pcicfg2 =
	    (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;

	if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
		/* XXX */
	} else {
		/* Reset Bus Arbiter */
		tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
		/* Enable Bus Arbiter */
		tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
	}