galileo.c

LINUX 2.6.17.4的源码

	GT_WRITE(PCI_CFG_ADR, SET_CONFIG_BITS(0, 0, where));

	GT_WRITE(PCI_CFG_DATA, val);
	return 0;
}

/* We exclude the galileo and slot 31, the galileo because I don't know how to stop
 * the setup code shagging up the setup I have done on it, and 31 because the whole
 * thing locks up if you try to access that slot (which doesn't exist of course anyway
 */

#define EXCLUDED_DEV(dev) ((dev->bus->number==0) && ((PCI_SLOT(dev->devfn)==0) || (PCI_SLOT(dev->devfn) == 31)))

static int galileo_read_config_byte(struct pci_dev *dev, int where,
				    u8 * val)
{

        
	/* I suspect this doesn't work because this drives a special cycle ? */
	if (EXCLUDED_DEV(dev)) {
		*val = 0xff;
		return PCIBIOS_SUCCESSFUL;
	}
	/* Start the config cycle */
	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
	/* Read back the result */
	*val = GT_READ_BYTE(PCI_CFG_DATA + (where & 3));

	return PCIBIOS_SUCCESSFUL;
}


static int galileo_read_config_word(struct pci_dev *dev, int where,
				    u16 * val)
{

        if (EXCLUDED_DEV(dev)) {
		*val = 0xffff;
		return PCIBIOS_SUCCESSFUL;
	}

	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
	*val = GT_READ_SHORT(PCI_CFG_DATA + (where & 2));

	return PCIBIOS_SUCCESSFUL;
}


static int galileo_read_config_dword(struct pci_dev *dev, int where,
				     u32 * val)
{
	if (EXCLUDED_DEV(dev)) {
		*val = 0xffffffff;
		return PCIBIOS_SUCCESSFUL;
	}

	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));
	*val = GT_READ(PCI_CFG_DATA);

	return PCIBIOS_SUCCESSFUL;
}

static int galileo_write_config_byte(struct pci_dev *dev, int where,
				     u8 val)
{
	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));

	GT_WRITE_BYTE(PCI_CFG_DATA + (where & 3), val);

	return PCIBIOS_SUCCESSFUL;
}


static int galileo_write_config_word(struct pci_dev *dev, int where,
				     u16 val)
{
	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));

	GT_WRITE_SHORT(PCI_CFG_DATA + (where & 2), val);

	return PCIBIOS_SUCCESSFUL;
}

static int galileo_write_config_dword(struct pci_dev *dev, int where,
				      u32 val)
{
	GT_WRITE(PCI_CFG_ADR, CONFIG_CMD(dev, where));

	GT_WRITE(PCI_CFG_DATA, val);

	return PCIBIOS_SUCCESSFUL;
}

static struct pci_ops pci_config_ops = {
	galileo_read_config_byte,
	galileo_read_config_word,
	galileo_read_config_dword,
	galileo_write_config_byte,
	galileo_write_config_word,
	galileo_write_config_dword
};


/* Everything hangs off this */
static struct pci_bus *pci_root_bus;


static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
{
	return PCI_SLOT(dev->devfn);
}

static int __init map_od_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
	/* Slot 1: Galileo 
	 * Slot 2: PCI Slot 1
	 * Slot 3: PCI Slot 2
	 * Slot 4: ESS
	 */
	switch (slot) {
	case 2: 
		return OVERDRIVE_PCI_IRQ1;
	case 3:
		/* Note this assumes you have a hacked card in slot 2 */
		return OVERDRIVE_PCI_IRQ2;
	case 4:
		return OVERDRIVE_ESS_IRQ;
	default:
		/* printk("PCI: Unexpected IRQ mapping request for slot %d\n", slot); */
		return -1;
	}
}



void __init
pcibios_fixup_pbus_ranges(struct pci_bus *bus, struct pbus_set_ranges_data *ranges)
{
        ranges->io_start -= bus->resource[0]->start;
        ranges->io_end -= bus->resource[0]->start;
        ranges->mem_start -= bus->resource[1]->start;
        ranges->mem_end -= bus->resource[1]->start;
}                                                                                

static void __init pci_fixup_ide_bases(struct pci_dev *d)
{
	int i;

	/*
	 * PCI IDE controllers use non-standard I/O port decoding, respect it.
	 */
	if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
		return;
	printk("PCI: IDE base address fixup for %s\n", pci_name(d));
	for(i=0; i<4; i++) {
		struct resource *r = &d->resource[i];
		if ((r->start & ~0x80) == 0x374) {
			r->start |= 2;
			r->end = r->start;
		}
	}
}
DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);

void __init pcibios_init(void)
{
	static struct resource galio,galmem;

        /* Allocate the registers used by the Galileo */
        galio.flags = IORESOURCE_IO;
        galio.name  = "Galileo GT64011";
        galmem.flags = IORESOURCE_MEM|IORESOURCE_PREFETCH;
        galmem.name  = "Galileo GT64011 DRAM";

        allocate_resource(&ioport_resource, &galio, 256,
		    GT64111_IO_BASE_ADDRESS,GT64111_IO_BASE_ADDRESS+256, 256, NULL, NULL);
        allocate_resource(&iomem_resource, &galmem,PCI_DRAM_SIZE,
		    PHYSADDR(PCI_DRAM_BASE), PHYSADDR(PCI_DRAM_BASE)+PCI_DRAM_SIZE, 
			     PCI_DRAM_SIZE, NULL, NULL);

  	/* ok, do the scan man */
	pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);

        pci_assign_unassigned_resources();
	pci_fixup_irqs(no_swizzle, map_od_irq);

#ifdef TEST_DRAM
        printk("Testing PCI DRAM - ");
	if(test_dram(PCI_DRAM_BASE,PCI_DRAM_SIZE)) {
		printk("Passed\n");
	}else {
		printk("FAILED\n");
	}
#endif

}

char * __init pcibios_setup(char *str)
{
	return str;
}



int pcibios_enable_device(struct pci_dev *dev)
{

	u16 cmd, old_cmd;
	int idx;
	struct resource *r;

	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	old_cmd = cmd;
	for (idx = 0; idx < 6; idx++) {
		r = dev->resource + idx;
		if (!r->start && r->end) {
			printk(KERN_ERR
			       "PCI: Device %s not available because"
			       " of resource collisions\n",
			       pci_name(dev));
			return -EINVAL;
		}
		if (r->flags & IORESOURCE_IO)
			cmd |= PCI_COMMAND_IO;
		if (r->flags & IORESOURCE_MEM)
			cmd |= PCI_COMMAND_MEMORY;
	}
	if (cmd != old_cmd) {
		printk("PCI: enabling device %s (%04x -> %04x)\n",
		       pci_name(dev), old_cmd, cmd);
		pci_write_config_word(dev, PCI_COMMAND, cmd);
	}
	return 0;

}

/* We should do some optimisation work here I think. Ok for now though */
void __init pcibios_fixup_bus(struct pci_bus *bus)
{

}

void pcibios_align_resource(void *data, struct resource *res,
			    unsigned long size)
{
}

void __init pcibios_update_resource(struct pci_dev *dev, struct resource *root,
			     struct resource *res, int resource)
{

	unsigned long where, size;
	u32 reg;
	

	printk("PCI: Assigning %3s %08lx to %s\n",
	       res->flags & IORESOURCE_IO ? "IO" : "MEM",
	       res->start, dev->name);

	where = PCI_BASE_ADDRESS_0 + resource * 4;
	size = res->end - res->start;

	pci_read_config_dword(dev, where, &reg);
	reg = (reg & size) | (((u32) (res->start - root->start)) & ~size);
	pci_write_config_dword(dev, where, reg);
}


void __init pcibios_update_irq(struct pci_dev *dev, int irq)
{
	printk("PCI: Assigning IRQ %02d to %s\n", irq, dev->name);
	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}

/*
 *  If we set up a device for bus mastering, we need to check the latency
 *  timer as certain crappy BIOSes forget to set it properly.
 */
unsigned int pcibios_max_latency = 255;

void pcibios_set_master(struct pci_dev *dev)
{
	u8 lat;
	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
	if (lat < 16)
		lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
	else if (lat > pcibios_max_latency)
		lat = pcibios_max_latency;
	else
		return;
	printk("PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
}