pci-auto.c

LINUX 2.6.17.4的源码

	/* We don't support prefetchable memory for now, so disable */
	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
				PCI_PREF_MEMORY_BASE, 0);
	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
				PCI_PREF_MEMORY_LIMIT, 0);
}

static void __init
pciauto_postscan_setup_bridge(struct pci_channel *hose,
			      int top_bus,
			      int current_bus,
			      int pci_devfn,
			      int sub_bus)
{
	u32 temp;

	/*
	 * [jsun] we always bump up baselines a little, so that if there
	 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
	 * spaces.
	 */
	pciauto_lower_memspc += 1;
	pciauto_lower_iospc += 1;

	/* Configure bus number registers */
	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
				PCI_SUBORDINATE_BUS, sub_bus);

	/* Set upper limit of address range behind bridge. */
	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
		PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
		PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
	early_write_config_word(hose, top_bus, current_bus, pci_devfn,
		PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);

	/* Align memory and I/O to 1MB and 4KB boundaries. */
	pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
		& ~(0x100000 - 1);
	pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
		& ~(0x1000 - 1);

	/* Enable memory and I/O accesses, enable bus master */
	early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_COMMAND, &temp);
	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
		| PCI_COMMAND_MASTER);
}

static void __init
pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
			int top_bus,
			int current_bus,
			int pci_devfn,
			int sub_bus)
{
	/* Configure bus number registers */
	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
				PCI_PRIMARY_BUS, current_bus);
	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
				PCI_SECONDARY_BUS, sub_bus + 1);
	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
				PCI_SUBORDINATE_BUS, 0xff);

	/* Align memory and I/O to 4KB and 4 byte boundaries. */
	pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
		& ~(0x1000 - 1);
	pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
		& ~(0x4 - 1);

	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_CB_IO_BASE_0, pciauto_lower_iospc);
}

static void __init
pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
			int top_bus,
			int current_bus,
			int pci_devfn,
			int sub_bus)
{
	u32 temp;

#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
	/*
	 * [jsun] we always bump up baselines a little, so that if there
	 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
	 * spaces.
	 */
	pciauto_lower_memspc += 1;
	pciauto_lower_iospc += 1;
#endif

	/*
	 * Configure subordinate bus number.  The PCI subsystem
	 * bus scan will renumber buses (reserving three additional
	 * for this PCI<->CardBus bridge for the case where a CardBus
	 * adapter contains a P2P or CB2CB bridge.
	 */

	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
				PCI_SUBORDINATE_BUS, sub_bus);

	/*
	 * Reserve an additional 4MB for mem space and 16KB for
	 * I/O space.  This should cover any additional space
	 * requirement of unusual CardBus devices with
	 * additional bridges that can consume more address space.
	 *
	 * Although pcmcia-cs currently will reprogram bridge
	 * windows, the goal is to add an option to leave them
	 * alone and use the bridge window ranges as the regions
	 * that are searched for free resources upon hot-insertion
	 * of a device.  This will allow a PCI<->CardBus bridge
	 * configured by this routine to happily live behind a
	 * P2P bridge in a system.
	 */
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
	pciauto_lower_memspc += 0x00400000;
	pciauto_lower_iospc += 0x00004000;
#endif

	/* Align memory and I/O to 4KB and 4 byte boundaries. */
	pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
		& ~(0x1000 - 1);
	pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
		& ~(0x4 - 1);
	/* Set up memory and I/O filter limits, assume 32-bit I/O space */
	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);

	/* Enable memory and I/O accesses, enable bus master */
	early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_COMMAND, &temp);
	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
		PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
		PCI_COMMAND_MASTER);
}

#define	PCIAUTO_IDE_MODE_MASK		0x05

static int __init
pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
{
	int sub_bus;
	u32 pci_devfn, pci_class, cmdstat, found_multi=0;
	unsigned short vid, did;
	unsigned char header_type;
	int devfn_start = 0;
	int devfn_stop = 0xff;

	sub_bus = current_bus;
	
	if (hose->first_devfn)
		devfn_start = hose->first_devfn;
	if (hose->last_devfn)
		devfn_stop = hose->last_devfn;
	
	for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {

		if (PCI_FUNC(pci_devfn) && !found_multi)
			continue;

		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
				       PCI_VENDOR_ID, &vid);

		if (vid == 0xffff) continue;

		early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
				       PCI_HEADER_TYPE, &header_type);

		if (!PCI_FUNC(pci_devfn))
			found_multi = header_type & 0x80;

		early_read_config_word(hose, top_bus, current_bus, pci_devfn,
				       PCI_DEVICE_ID, &did);

		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
					PCI_CLASS_REVISION, &pci_class);

		DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
			current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
			pci_class >> 16, vid, did);
		if (pci_class & 0xff)
			DBG(" (rev %.2x)", pci_class & 0xff);
		DBG("\n");

		if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
			DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
				current_bus, sub_bus + 1);
#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
			pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1);
#endif
			pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
						     pci_devfn, sub_bus);
			DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
				sub_bus + 1,
				pciauto_lower_iospc, pciauto_lower_memspc);
			sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
			DBG("Back to bus %.2x\n", current_bus);
			pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
							pci_devfn, sub_bus);
			continue;
		} else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
			DBG("  CARDBUS  Bridge: primary=%.2x, secondary=%.2x\n",
				current_bus, sub_bus + 1);
			DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
			/* Place CardBus Socket/ExCA registers */
			pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
 
			pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
					current_bus, pci_devfn, sub_bus);
 
			DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
				sub_bus + 1,
				pciauto_lower_iospc, pciauto_lower_memspc);
			sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
			DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
			pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
					current_bus, pci_devfn, sub_bus);
			continue;
		} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {

			unsigned char prg_iface;

			early_read_config_byte(hose, top_bus, current_bus,
				pci_devfn, PCI_CLASS_PROG, &prg_iface);
			if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
				DBG("Skipping legacy mode IDE controller\n");
				continue;
			}
		}

		/*
		 * Found a peripheral, enable some standard
		 * settings
		 */
		early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
					PCI_COMMAND, &cmdstat);
		early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
					 PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
					 PCI_COMMAND_MEMORY |
					 PCI_COMMAND_MASTER);
#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
		early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
					PCI_LATENCY_TIMER, 0x80);
#endif

		/* Allocate PCI I/O and/or memory space */
		pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
	}
	return sub_bus;
}

int __init
pciauto_assign_resources(int busno, struct pci_channel *hose)
{
	/* setup resource limits */
	io_resource_inuse = hose->io_resource;
	mem_resource_inuse = hose->mem_resource;

	pciauto_lower_iospc = io_resource_inuse->start;
	pciauto_upper_iospc = io_resource_inuse->end + 1;
	pciauto_lower_memspc = mem_resource_inuse->start;
	pciauto_upper_memspc = mem_resource_inuse->end + 1;
	DBG("Autoconfig PCI channel 0x%p\n", hose);
	DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
		busno, pciauto_lower_iospc, pciauto_upper_iospc, 
		pciauto_lower_memspc, pciauto_upper_memspc);

	return pciauto_bus_scan(hose, busno, busno);
}