ctrl.asm

DSP的例程

	.title	"TMS320C2xx PROCESSOR SELFCHECK -- CONTROL INSTRUCTIONS TEST"
	.length	60
	.width	120
	.option	X
************************************************************
* CONTROL INSTRUCTIONS TEST                                *
*                                                          *
* This routine checks various control instructions.        *
*                                                          *
* Written by:                                              *
*                                                          *
* Release Version 1.0                                      *
*                                                          *
************************************************************
	.def	ctrl
	.nolist
	.copy	"options.h"
	.copy	"memmap.h"
	.list

BITCODE1	.set	6h
BITCODE2	.set	7h

	.text
ctrl	.set	$ + SS

*
* Test ST0 and ST1 register control
*

; Preliminary setup
	LDP	#0h		; data page @ 0h
	MAR	*,AR0		; ARP --> AR0
	LAR	AR0,#TEMP00	; AR0 points to TEMP00
	LAR	AR1,#TEMP04	; AR1 points to TEMP04
	SPLK	#5555h,TEMP00	; data(TEMP00) = 5555h
	LACC	*,16		; ACC = 55550000h
	SACH	*+,1		; data(TEMP00)=aaaah & AR0 points to TEMP01
	SACH	TEMP01		; data(TEMP01)=5555h

; Exercise ST1 - direct addressing LST & SST instructions
	LST	#1,TEMP00	; write aaaah to ST1
	SST	#1,TEMP02	; data(TEMP02) = ST1 = abeeh

				; *** WARNING ABOVE ***  
				; Simulator bug produces ST1 = abaeh

; Exercise ARP to ARB copy on ARP redirection        
	MAR	*,AR4		; ARP --> AR4
	MAR	*,AR0		; ARP --> AR0
	SST	#1,TEMP03	; data(TEMP03) = ST1 = 8beeh

				; *** WARNING ABOVE ***  
				; Simulator bug produces ST1 = 8baeh

; Exercise ST1 - indirect addressing LST & SST instructions
	LST	#1,*		; write 5555h to ST1
	MAR	*,AR1		; previous instruction corrupts ARP
	SST	#1,*		; data(TEMP04) = ST1 = 55fdh

; Exercise ST0
	SETC	INTM		; this instruction for testing CLRC INTM
	CLRC	INTM		; LST shouldn't affect INTM
	LST	#0,TEMP00	; write aaaah to ST0
	SST	#0,TEMP05	; data(TEMP05) = ST0 = acaah

; Exercise ARB to ARP copy on "LST #1" instruction
	LDP	#0h		; data page @ 0h
	LST	#1,TEMP01	; write 5555h to ST1
	SST	#0,TEMP06	; data(TEMP05) = 4c00h 

; Finish exercising ST0
	LST	#0,TEMP01	; write 5555h to ST0
	SST	#0,TEMP07	; data(TEMP07) = ST0 = 5555h

; Check SETC and CLRC instructions (currently, ST0 = 5555h, ST1 = 55fdh)
	CLRC	CNF		; ST1 = 45fdh
	SETC	TC		; ST1 = 4dfdh
	CLRC	SXM		; ST1 = 49fdh
	SETC	C		; ST1 = 4bfdh
	CLRC	XF		; ST1 = 4bedh
	SST	#1,TEMP08	; data(TEMP08) = ST1 = 4bedh
	SETC	XF		; ST1 = 4bfdh
	CLRC	C		; ST1 = 49fdh
	SETC	SXM		; ST1 = 4dfdh
	CLRC	TC		; ST1 = 45fdh
	SST	#1,TEMP09	; data(TEMP09) = ST1 = 45fdh
	SETC	OVM		; ST0 = 5d55h
	SETC	INTM		; ST0 = 5f55h
	SST	#0,TEMP0A	; data(TEMP0A) = ST0 = 5f55h
	CLRC	OVM		; ST0 = 5755h
	SST	#0,TEMP0B	; data(TEMP0B) = ST0 = 5755h

; Test for the correct answers
	LDP	#0h		; data page @ 0h

	.if SIMULATOR != 1	; conditional due to simulator bug
	LACC	TEMP02		; load stored result
	SUB	#0abeeh		; subtract correct answer
	BCND	erctrl1,NEQ	; if ACC != 0 then ST1 error
	LACC	TEMP03		; load stored result
	SUB	#8beeh		; subtract correct answer
	BCND	erctrl1,NEQ	; if ACC != 0 then ST1 error
	.endif

	LACC	TEMP04		; load stored result
	SUB	#55fdh		; subtract correct answer
	BCND	erctrl1,NEQ	; if ACC != 0 then ST1 error
	LACC	TEMP05		; load stored result
	SUB	#0acaah		; subtract correct answer
	BCND	erctrl2,NEQ	; if ACC != 0 then ST0 error
	LACC	TEMP06		; load stored result
	SUB	#4c00h		; subtract correct answer
	BCND	erctrl2,NEQ	; if ACC != 0 then ST0 error
	LACC	TEMP07		; load stored result
	SUB	#5555h		; subtract correct answer
	BCND	erctrl2,NEQ	; if ACC != 0 then ST0 error
	LACC	TEMP08		; load stored result
	SUB	#4bedh		; subtract correct answer
	BCND	erctrl3,NEQ	; if ACC != 0 then SETC/CLRC error
	LACC	TEMP09		; load stored result
	SUB	#45fdh		; subtract correct answer
	BCND	erctrl3,NEQ	; if ACC != 0 then ST0 error
	LACC	TEMP0A		; load stored result
	SUB	#5f55h		; subtract correct answer
	BCND	erctrl3,NEQ	; if ACC != 0 then ST0 error
	LACC	TEMP0B		; load stored result
	SUB	#5755h		; subtract correct answer
	BCND	erctrl3,NEQ	; if ACC != 0 then ST0 error

*
* Test BIT and BITT instructions
*
	BIT	TEMP00,BITCODE1	; test TEMP00
	BCND	erctrl4,NTC	; if TC bit = 0 then error
	MAR	*,AR0		; ARP --> AR0
	LAR	AR0,#TEMP00	; AR0 points to TEMP00
	BIT	*+,BITCODE2	; test TEMP00 and AR0 points to TEMP01
	BCND	erctrl4,TC	; if TC bit != 0 then error
	LT	TEMP00		; TREG = aaaah       
	BITT	TEMP00		; test TEMP00
	BCND	erctrl4,NTC	; if TC bit = 0 then error
	LT	*-		; TREG = 5555h and AR0 points to TEMP00
	BITT	*		; test TEMP00
	BCND	erctrl4,TC	; if TC bit != 0 then error

*
* Check stack operations
*
; save current stack in data memory
	MAR	*,AR1		; ARP --> AR1
	LAR	AR1,#TEMP07	; AR1 points to TEMP07
	RPT	#6h		; execute next instruction 7 times
	POPD	*+		; save top 7 stack levels to data memory
	POPD	*,AR0		; save final stack entry to data memory

; exercise all 8 stack levels
	LDP	#0h		; data page @ 0h                    
	LACL	#55h		; ACC = 55h
	SACL	TEMP00		; data(TEMP00) = 55h
	SACL	TEMP01,1	; data(TEMP01) = aah
	PSHD	*		; push data(TEMP00) = 55h onto stack
	PSHD	TEMP01		; push data(TEMP01) = aah onto stack
	SPLK	#1h,TEMP02	; data(TEMP02) = 1h             
	RPT	TEMP02		; execute next instruction twice
	SFL			; ACC --> aah --> 154h
	PUSH			; push ACC onto stack
	SFL			; ACC = 2a8h
	PUSH			; push ACC onto stack
	SFL			; ACC = 550h
	PUSH			; push ACC onto stack
	SFL			; ACC = aa0h
	PUSH			; push ACC onto stack
	SFL			; ACC = 1540h
	PUSH			; push ACC onto stack
	SFL			; ACC = 2a80h        
	PUSH			; push ACC onto stack
	SPLK	#5h,*		; data(TEMP00) = 4h
	RPT	*		; execute next instruction 6 times
	POPD	*+		; pop stack into TEMP00 through TEMP05
	POPD	TEMP06		; data(TEMP06) = aah
	POP			; ACC = 55h
	RPT	#5h		; execute next instruction 6 times
	ADD	*-		; add to ACC
	ADD	*,AR1		; add last value & ARP --> AR1
	SUB	#54abh		; subtract correct checksum answer
	BCND	erctrl5,NEQ	; if ACC != 0 then error
	
; restore original stack from data memory
	RPT	#7h		; execute next instruction 8 times
	PSHD	*-		; restore all 8 stack levels

	RET			; test passes

*
* ERROR HANDLERS
*
erctrl1	.set	$ + SS

	LACL	#30h		; ST1 load/store error
	RET			; test fails
;
erctrl2	.set	$ + SS

	LACL	#31h		; ST0 load/store error
	RET			; test fails
;
erctrl3	.set	$ + SS

	LACL    #32h		; SETC or CLRC error
	RET			; test fails
;
erctrl4	.set	$ + SS

	LACL	#33h		; BIT or BITT error
	RET			; test fails
;
erctrl5	.set	$ + SS

	LACL	#34h		; stack operations error
	RET			; test fails