data.asm

DSP的例程

	.title	"TMS320C2xx PROCESSOR SELFCHECK -- DATA MEMORY OPERATIONS"
	.length	60
	.width	120
	.option	X
************************************************************
* DATA MEMORY OPERATIONS TEST                              *
*                                                          *
* This routine tests the operation and paths for data      *
* memory operations in the direct and indirect addressing  *
* modes.  It also test the auxillary registers.            *
*                                                          *
* Written by:                                              *
*                                                          *
* Release Version 1.0                                      *
*                                                          *
************************************************************
	.def	data
	.nolist
	.copy	"options.h"
	.copy	"memmap.h"
	.list

DMA0	.set	0h		; 1st address in current data page
DMA1	.set	1h		; 2nd address in current data page
B0PROG	.set	0ff00h		; 1st address in B0 program block
B0DATA	.set	200h		; 1st address in B0 data block
B1DATA	.set	300h		; 1st address in B1 data block

	.text
data	.set	$+SS

*
* TEST DIRECT MEMORY ADDRESSING DATA OPERATIONS
*
; preliminary setup
	CLRC	CNF		; map RAM block B0 to data space

; The following segment targets the BLDD and DMOV instructions
	LDP	#4h		; data page @ 200h
	SPLK	#6h,DMA0	; data(200h) = 6h
	LACC	#0aaaah		; load test pattern
	SACL	DMA1		; data(201h) = aaaah
	BLDD	DMA1,#B1DATA	; data(300h) = aaaah
	LDP	DMA0		; data page @ 300h
	DMOV	DMA0		; copy data(300h) to 301h
	LDP	#4h		; data page @ 200h
	BLDD	#(B1DATA+1),DMA0	; data(200h) = aaaah
	SUB	DMA0		; subtract data(200h)
	BCND	erdata1,NEQ	; if ACC != 0 test fails

; The following segment targets the BLPD, TBLR, and TBLW instructions
data1	.set	$+SS		; keep with next line (NOP)

	NOP			; progam instruction @ data1 = NOP
	MAR	*,AR0		; ARP --> AR0
	LAR	AR0,#B0DATA	; AR0 points to 200h
	SPLK	#6h,DMA0	; data(200h) = 6h
	LDP	*		; data page @ 300h
	BLPD	#data1,DMA0	; data(300h) = 8b00h (NOP opcode)
	SETC	CNF		; map RAM block B0 to program space
	LACC	#B0PROG		; ACC points to start of B0 program block
	TBLW	DMA0		; data(ff00h)@prog = 8b00h
	TBLR	DMA1		; data(301h) = 8B00h
	CLRC	CNF		; return RAM block B0 to data space
	LACC	DMA1		; ACC = 8b00h
	SUB	#8b00h		; subtract
	BCND	erdata2,NEQ	; if ACC != 0 test fails

*
* TEST AUXILLARY REGISTER OPERATIONS
*
; preliminary setup
	LDP	#0h		; data page @ 0h

; Test AR0 first
	MAR	*,AR0		; ARP --> AR0
	SPLK	#7fffh,TEMP00	; data(TEMP00) = 7fffh
	LAR	AR0,TEMP00	; AR0 = 7fffh
	MAR	*+		; AR0 = 8000h (worst case ARAU carry)
	SBRK	#2h		; AR0 = 7ffeh
	SAR	AR0,TEMP00	; TEMP00 = 7ffeh
	LACL	TEMP00		; ACC = 7ffeh
	SUB	#7ffeh		; subtract
	BCND	erdata10,NEQ	; if ACC != 0, test fails

	LAR	AR0,#8000h	; AR0 = 8000h
	MAR	*-		; AR0 = 7fffh (worst case ARAU carry)
	ADRK	#2h		; AR0 = 8001h
	MAR	*,AR1		; ARP --> AR1
	LAR	AR1,#TEMP00	; AR1 points to TEMP00
	SAR	AR0,*,AR0	; TEMP00 = 8001h & ARP --> AR0
	LACC	TEMP00		; ACC = 8001h
	SUB	#8001h		; subtract
	BCND	erdata10,NEQ	; if ACC != 0, test fails

; Make sure "CMPR 0" instruction works before checking AR1 - AR7
	CMPR	0		; compare AR0 to itself
	BCND	erdata3,NTC	; error if TC bit not set

; Now test AR1 through AR7
	SPLK	#7fffh,TEMP00	; data(60h) = 7fffh

	LAR	AR0,#TEMP00	; AR0 points to TEMP00
	LAR	AR1,*,AR1	; AR1 = 7fffh, & ARP --> AR1 (LAR indirect)
	CALL	aux		; call auxilary register test
	BCND	erdata11,NEQ	; abort if previous ARn failed

	MAR	*,AR2		; ARP --> AR2
	LAR	AR2,TEMP00	; AR2 = 7fffh 
	CALL	aux		; call auxilary register test
	BCND	erdata12,NEQ	; abort if previous ARn failed

	MAR	*,AR3		; ARP --> AR3
	LAR	AR3,TEMP00	; AR3 = 7fffh (LAR direct) 
	CALL	aux		; call auxilary register test
	BCND	erdata13,NEQ	; abort if previous ARn failed

	MAR	*,AR4		; ARP --> AR4
	LAR	AR4,TEMP00	; AR4 = 7fffh
	CALL	aux		; call auxilary register test
	BCND	erdata14,NEQ	; abort if previous ARn failed

	MAR	*,AR5		; ARP --> AR5
	LAR	AR5,TEMP00	; AR5 = 7fffh
	CALL	aux		; call auxilary register test
	BCND	erdata15,NEQ	; abort if previous ARn failed

	MAR	*,AR6		; ARP --> AR6
	LAR	AR6,TEMP00	; AR6 = 7fffh
	CALL	aux		; call auxilary register test
	BCND	erdata16,NEQ	; abort if previous ARn failed

	MAR	*,AR7		; ARP --> AR7
	LAR	AR7,TEMP00	; AR7 = 7fffh
	CALL	aux		; call auxilary register test
	BCND	erdata17,NEQ	; abort if previous ARn failed
*
* TEST INDIRECT MEMORY ADDRESSING DATA OPERATIONS
*
; preliminary setup
	LAR	AR0,#200h	; Load auxillary registers.
	LAR	AR1,#201h	;  No two consecutive registers point
	LAR	AR2,#300h	;  to same address to catch failure
	LAR	AR3,#200h	;  of ARP redirection.
	LAR	AR4,#300h	;
	LAR	AR5,#TEMP00	; AR5 points to address TEMP00
	LAR	AR6,#300h	;
	LAR	AR7,#301h	;

	SPLK	#B0PROG,TEMP00	; data(TEMP00) = 0ff00h

; The following segment targets the LACT, BLDD and DMOV instructions
	MAR	*,AR0		; ARP --> AR0
	SPLK	#1111h,*	; data(200h) = 1111h
	LT	*,AR1		; TREG = 1111h
	LDP	#4h		; data page @ 200h
	LACT	DMA0		; ACC = 2222h
	SACL	*		; data(201h) = 2222h
	BLDD	*,#B1DATA,AR2	; data(300h) = 2222h
	DMOV	*,AR3		; copy data(300h) to 301h
	BLDD	#(B1DATA+1),*	; data(200h) = 2222h
	LACT	*,AR4		; ACC = 4444h      
	SUB	#4444h		; subtract
	BCND	erdata4,NEQ	; if ACC != 0 test fails

; The following segment targets the BLPD, TBLR, and TBLW instructions
data2	.set	$+SS		; keep with next line (MAR) 

	MAR	7fh		; instruction @ data2 = MAR (direct addr mode)
	BLPD	#data2,*,AR5	; data(300h)=8b7fh (MAR 7fh opcode)
	SETC	CNF		; map RAM block B0 to program space
	LACL	*,AR6		; ACC = 0ff00h (start addr of B0 program block)
	TBLW	*,AR7		; data(ff00h)@prog = 8b7fh
	TBLR	*		; data(301h) = 8b7fh
	CLRC	CNF		; return RAM block B0 to data space
	LACC	*		; ACC = 8b7fh
	SUB	#8b7fh		; subtract
	BCND	erdata5,NEQ	; if ACC != 0 test fails

	RET			; test passes
*
* ERROR HANDLERS
*
erdata1	.set	$+SS

	LACL	#20h		; direct addr error (BLDD, DMOV)
	RET			; test fails
;
erdata2	.set	$+SS

	LACL	#21h		; direct addr error (BLPD, TBLR, TBLW)
	RET			; test fails
;
erdata3	.set	$+SS

	LACL	#22h		; CMPR instruction error
	RET			; test fails
;
erdata4	.set	$+SS

	LACL	#23h		; LACT or indirect addr error (BLDD, DMOV)
	RET			; test fails
;
erdata5	.set	$+SS

	LACL	#24h		; indirect addr error (BLPD, TBLR, TBLW)
	RET			; test fails
;
erdata10	.set	$+SS

	LACL	#28h		; AR0 error 
	RET			; test fails
;
erdata11	.set	$+SS

	LACL	#29h		; AR1 error 
	RET			; test fails
;
erdata12	.set	$+SS

	LACL	#2ah		; AR2 error 
	RET			; test fails
;
erdata13	.set	$+SS

	LACL	#2bh		; AR3 error 
	RET			; test fails
;
erdata14	.set	$ + SS

	LACL	#2ch		; AR4 error 
	RET			; test fails
;
erdata15	.set	$ + SS

	LACL	#2dh		; AR5 error 
	RET			; test fails
;
erdata16	.set	$ + SS

	LACL	#2eh		; AR6 error 
	RET			; test fails
;
erdata17	.set	$ + SS

	LACL	#2fh		; AR7 error 
	RET			; test fails

	.page
************************************************************
* SUBROUTINE aux                                           *
*                                                          *
* This subroutine is called to test each of auxillary      *
* registers 1 through 7.                                   *
*                                                          *
************************************************************
aux	.set	$+SS

; preliminary setup        
	LAR	AR0,#7fffh	; AR0 = 7fffh

; Exercise arithmetic operations of ARAU
	MAR	*+		; AR(ARP) = 8000h (worst case ARAU carry)
	MAR	*BR0-		; AR(ARP) = c000h
	MAR	*0+		; AR(ARP) = 3fffh
	MAR	*BR0+		; AR(ARP) = 5fffh
	ADRK	#1h		; AR(ARP) = 6000h
	MAR	*0-		; AR(ARP) = e001h
	MAR	*-		; AR(ARP) = e000h
	SBRK	#2h		; AR(ARP) = dffeh

; Check for an error        
	LAR	AR0,#0dffeh	; AR0 = dffeh (the correct answer)
	CMPR	0		; TC bit set if AR(ARP) == AR0
	BCND	eraux,NTC	; error if TC bit not set
	CMPR	1		; TC bit set if AR(ARP) < AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	2		; TC bit set if AR(ARP) > AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	3		; TC bit set if AR(ARP) != AR0
	BCND	eraux,TC	; error if TC bit set

	LAR	AR0,#0dffdh	; AR0 = dffdh (the wrong answer)
	CMPR	0		; TC bit set if AR(ARP) == AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	1		; TC bit set if AR(ARP) < AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	2		; TC bit set if AR(ARP) > AR0
	BCND	eraux,NTC	; error if TC bit not set
	CMPR	3		; TC bit set if AR(ARP) != AR0
	BCND	eraux,NTC	; error if TC bit not set

	LAR	AR0,#0dfffh	; AR0 = dfffh (the wrong answer)
	CMPR	0		; TC bit set if AR(ARP) == AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	1		; TC bit set if AR(ARP) < AR0
	BCND	eraux,NTC	; error if TC bit not set
	CMPR	2		; TC bit set if AR(ARP) > AR0
	BCND	eraux,TC	; error if TC bit set
	CMPR	3		; TC bit set if AR(ARP) != AR0
	BCND	eraux,NTC	; error if TC bit not set

	RET			; test passes
;
eraux	.set	$+SS

	LACL	#1h		; return arbitrary non-zero ACC on error
	RET			; test fails