📄 smart_ci.lst
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A51 MACRO ASSEMBLER SMART_CI 08/06/2006 09:11:04 PAGE 1
MACRO ASSEMBLER A51 V7.07
OBJECT MODULE PLACED IN SMART_CI.OBJ
ASSEMBLER INVOKED BY: D:\Keil\C51\BIN\A51.EXE SMART_CI.ASM SET(SMALL) DEBUG EP
LOC OBJ LINE SOURCE
1 ; D12CI.ASM generated and modified from: D12CI.C
2
3 $nomod51
4
5 NAME D12CI
6
0080 7 P0 DATA 080H
0090 8 P1 DATA 090H
00A0 9 P2 DATA 0A0H
00B0 10 P3 DATA 0B0H
00B4 11 T0 BIT 0B0H.4
00D6 12 AC BIT 0D0H.6
00B5 13 T1 BIT 0B0H.5
00AF 14 EA BIT 0A8H.7
00A8 15 IE DATA 0A8H
00B7 16 RD BIT 0B0H.7
00AC 17 ES BIT 0A8H.4
00B8 18 IP DATA 0B8H
0098 19 RI BIT 098H.0
00B2 20 INT0 BIT 0B0H.2
00D7 21 CY BIT 0D0H.7
0099 22 TI BIT 098H.1
00B3 23 INT1 BIT 0B0H.3
00BC 24 PS BIT 0B8H.4
0081 25 SP DATA 081H
00D2 26 OV BIT 0D0H.2
00B6 27 WR BIT 0B0H.6
0099 28 SBUF DATA 099H
0087 29 PCON DATA 087H
00A0 30 MCU_HOSTDREQ BIT 0A0H.0
0098 31 SCON DATA 098H
0089 32 TMOD DATA 089H
0088 33 TCON DATA 088H
0089 34 IE0 BIT 088H.1
008B 35 IE1 BIT 088H.3
00F0 36 B DATA 0F0H
00E0 37 ACC DATA 0E0H
00A9 38 ET0 BIT 0A8H.1
00AB 39 ET1 BIT 0A8H.3
008D 40 TF0 BIT 088H.5
008F 41 TF1 BIT 088H.7
009A 42 RB8 BIT 098H.2
008C 43 TH0 DATA 08CH
00A8 44 EX0 BIT 0A8H.0
0088 45 IT0 BIT 088H.0
008D 46 TH1 DATA 08DH
009B 47 TB8 BIT 098H.3
00AA 48 EX1 BIT 0A8H.2
008A 49 IT1 BIT 088H.2
00D0 50 P BIT 0D0H.0
009F 51 SM0 BIT 098H.7
008A 52 TL0 DATA 08AH
009E 53 SM1 BIT 098H.6
008B 54 TL1 DATA 08BH
009D 55 SM2 BIT 098H.5
00B9 56 PT0 BIT 0B8H.1
00BB 57 PT1 BIT 0B8H.3
00D3 58 RS0 BIT 0D0H.3
A51 MACRO ASSEMBLER SMART_CI 08/06/2006 09:11:04 PAGE 2
008C 59 TR0 BIT 088H.4
00D4 60 RS1 BIT 0D0H.4
008E 61 TR1 BIT 088H.6
00B8 62 PX0 BIT 0B8H.0
00BA 63 PX1 BIT 0B8H.2
0083 64 DPH DATA 083H
0082 65 DPL DATA 082H
009C 66 REN BIT 098H.4
00B0 67 RXD BIT 0B0H.0
00B1 68 TXD BIT 0B0H.1
00D5 69 F0 BIT 0D0H.5
00D0 70 PSW DATA 0D0H
71 ?PR?_D12_SetAddressEnable?D12CI SEGMENT CODE
72 ?DT?_D12_SetAddressEnable?D12CI SEGMENT DATA OVERLAYABLE
73 ?PR?_D12_SetEndpointEnable?D12CI SEGMENT CODE
74 ?DT?_D12_SetEndpointEnable?D12CI SEGMENT DATA OVERLAYABLE
75 ?PR?_D12_SetMode?D12CI SEGMENT CODE
76 ?DT?_D12_SetMode?D12CI SEGMENT DATA OVERLAYABLE
77 ?PR?_D12_SetDMA?D12CI SEGMENT CODE
78 ?DT?_D12_SetDMA?D12CI SEGMENT DATA OVERLAYABLE
79 ?PR?D12_GetDMA?D12CI SEGMENT CODE
80 ?PR?D12_ReadInterruptRegister?D12CI SEGMENT CODE
81 ?DT?D12_ReadInterruptRegister?D12CI SEGMENT DATA OVERLAYABLE
82 ?PR?_D12_SelectEndpoint?D12CI SEGMENT CODE
83 ?PR?_D12_ReadLastTransactionStatus?D12CI SEGMENT CODE
84 ?PR?_D12_ReadEndpointStatus?D12CI SEGMENT CODE
85 ?PR?_D12_SetEndpointStatus?D12CI SEGMENT CODE
86 ?DT?_D12_SetEndpointStatus?D12CI SEGMENT DATA OVERLAYABLE
87 ?PR?D12_SendResume?D12CI SEGMENT CODE
88 ?PR?D12_ReadCurrentFrameNumber?D12CI SEGMENT CODE
89 ?DT?D12_ReadCurrentFrameNumber?D12CI SEGMENT DATA OVERLAYABLE
90 ?PR?D12_ReadChipID?D12CI SEGMENT CODE
91 ?DT?D12_ReadChipID?D12CI SEGMENT DATA OVERLAYABLE
92 ?PR?_D12_ReadEndpoint?D12CI SEGMENT CODE
93 ?DT?_D12_ReadEndpoint?D12CI SEGMENT DATA OVERLAYABLE
94 ?PR?_D12_WriteEndpoint?D12CI SEGMENT CODE
95 ?DT?_D12_WriteEndpoint?D12CI SEGMENT DATA OVERLAYABLE
96 ?PR?_D12_AcknowledgeEndpoint?D12CI SEGMENT CODE
97 ?DT?_D12_AcknowledgeEndpoint?D12CI SEGMENT DATA OVERLAYABLE
98 EXTRN DATA (bEPPflags)
99 EXTRN CODE (?C_CSTOPTR)
100 EXTRN CODE (?C_CLDOPTR)
101 PUBLIC _D12_AcknowledgeEndpoint
102 PUBLIC ?_D12_WriteEndpoint?BYTE
103 PUBLIC _D12_WriteEndpoint
104 PUBLIC ?_D12_ReadEndpoint?BYTE
105 PUBLIC _D12_ReadEndpoint
106 PUBLIC D12_ReadChipID
107 PUBLIC D12_ReadCurrentFrameNumber
108 PUBLIC D12_SendResume
109 PUBLIC _D12_SetEndpointStatus
110 PUBLIC _D12_ReadEndpointStatus
111 PUBLIC _D12_ReadLastTransactionStatus
112 PUBLIC _D12_SelectEndpoint
113 PUBLIC D12_ReadInterruptRegister
114 PUBLIC _D12_SetDMA
115 PUBLIC D12_GetDMA
116 PUBLIC _D12_SetMode
117 PUBLIC _D12_SetEndpointEnable
118 PUBLIC _D12_SetAddressEnable
119
---- 120 RSEG ?DT?_D12_SetAddressEnable?D12CI
0000 121 ?_D12_SetAddressEnable?BYTE:
0000 122 bAddress?00: DS 1
0001 123 bEnable?00: DS 1
124
A51 MACRO ASSEMBLER SMART_CI 08/06/2006 09:11:04 PAGE 3
---- 125 RSEG ?DT?_D12_SetEndpointEnable?D12CI
0000 126 ?_D12_SetEndpointEnable?BYTE:
0000 127 bEnable?10: DS 1
128
---- 129 RSEG ?DT?_D12_SetMode?D12CI
0000 130 ?_D12_SetMode?BYTE:
0000 131 bConfig?20: DS 1
0001 132 bClkDiv?20: DS 1
133
---- 134 RSEG ?DT?_D12_SetDMA?D12CI
0000 135 ?_D12_SetDMA?BYTE:
0000 136 bMode?30: DS 1
137
---- 138 RSEG ?DT?D12_ReadInterruptRegister?D12CI
0000 139 ?D12_ReadInterruptRegister?BYTE:
0000 140 b1?41: DS 1
141
---- 142 RSEG ?DT?_D12_SetEndpointStatus?D12CI
0000 143 ?_D12_SetEndpointStatus?BYTE:
0000 144 bStalled?80: DS 1
145
---- 146 RSEG ?DT?D12_ReadCurrentFrameNumber?D12CI
0000 147 ?D12_ReadCurrentFrameNumber?BYTE:
0000 148 i?101: DS 2
149
---- 150 RSEG ?DT?D12_ReadChipID?D12CI
0000 151 ?D12_ReadChipID?BYTE:
0000 152 i?111: DS 2
153
---- 154 RSEG ?DT?_D12_ReadEndpoint?D12CI
0000 155 ?_D12_ReadEndpoint?BYTE:
0000 156 endp?120: DS 1
0001 157 len?120: DS 1
0002 158 buf?120: DS 3
0005 159 ORG 5
0005 160 i?121: DS 1
0006 161 j?121: DS 1
162
---- 163 RSEG ?DT?_D12_WriteEndpoint?D12CI
0000 164 ?_D12_WriteEndpoint?BYTE:
0000 165 endp?140: DS 1
0001 166 len?140: DS 1
0002 167 buf?140: DS 3
0005 168 ORG 5
0005 169 i?141: DS 1
170
---- 171 RSEG ?DT?_D12_AcknowledgeEndpoint?D12CI
0000 172 ?_D12_AcknowledgeEndpoint?BYTE:
0000 173 endp?150: DS 1
174
175 ; //*************************************************************************
176 ; //
177 ; // P H I L I P S P R O P R I E T A R Y
178 ; //
179 ; // COPYRIGHT (c) 1997 BY PHILIPS SINGAPORE.
180 ; // -- ALL RIGHTS RESERVED --
181 ; //
182 ; // File Name: D12CI.C
183 ; // Author: Wenkai Du
184 ; // Created: 8 Jun 98
185 ; // Modified:
186 ; // Revision: 2.2
187 ; //
188 ; //*************************************************************************
189 ; //
190 ; // 98/11/27 I/O mode Main endpoints read/write update (WK)
A51 MACRO ASSEMBLER SMART_CI 08/06/2006 09:11:04 PAGE 4
191 ; // 98/12/2 Added D12_ReadMainEndpoint (WK)
192 ; //*************************************************************************
193
194 ;
195 ; void D12_SetAddressEnable(unsigned char bAddress, unsigned char bEnable)
196
---- 197 RSEG ?PR?_D12_SetAddressEnable?D12CI
198 USING 0
0000 199 _D12_SetAddressEnable:
0000 8F00 F 200 MOV bAddress?00,R7
0002 8D00 F 201 MOV bEnable?00,R5
202 ; SOURCE LINE # 33
203 ; {
204 ; SOURCE LINE # 34
205 ; if(bEPPflags.bits.in_isr == 0)
206 ; SOURCE LINE # 35
0004 AF00 F 207 MOV R7,bEPPflags
0006 EF 208 MOV A,R7
0007 C4 209 SWAP A
0008 13 210 RRC A
0009 5407 211 ANL A,#07H
000B 20E002 212 JB ACC.0,?C0001
213 ; DISABLE;
214 ; SOURCE LINE # 36
000E C2AF 215 CLR EA
0010 216 ?C0001:
217 ;
218 ; outportb(D12_COMMAND, 0xD0);
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