seg7led_itf.v

自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,

//-------------------------------------------------------------------------------------------------
//       Copyright (c) 2006, SVA Central Research Academe Co., Ltd.
//                      All Rights Reserved
//    SVA Central Research Academe CONFIDENTIAL PROPRIETRAY
//    This is unpublished proprietary source code of SVA Central Research
//    Academe Inc.
//    The copyright notice above does not evidence any actual or intended
//    publication of such source code.
//-------------------------------------------------------------------------------------------------
// FILE NAME    : seg7led_itf.v
// TYPE         : Verilog-HDL RTL
// DEPARTMENT   : SVA Central Research Academe Digital Television Dept.
// AUTHOR       : He Jiangyuan
// EMAIL        :
//-------------------------------------------------------------------------------------------------
// Release/Revision History
// Version     Date           Author          Description
// 0.1.0       20080401       He Jiangyuan    Creat new
//-------------------------------------------------------------------------------------------------
// KEYWORDS     :
//-------------------------------------------------------------------------------------------------
// PURPOSE      : SEG7 LED Display Interface
//-------------------------------------------------------------------------------------------------
// REUSE ISSUES :
//-------------------------------------------------------------------------------------------------
//`define DEBUG

module SEG7LED_ITF(
//TEST
       `ifdef DEBUG
       TestTP0_T,
       `endif

//CLOCK & RESET
       clk,
       rstn,

//INPUT
       load,
       disable_en,
       bcd0,
       bcd1,
       bcd2,
       bcd3,

       dp0,
       dp1,
       dp2,
       dp3,

       seg_en0,
       seg_en1,
       seg_en2,
       seg_en3,
//OUTPUT
       seg7_bit,
       seg7_led
);

/******************* PARAMETER DECLARATION *********************/


/*********************** IO DECLARATION ************************/
input  clk;
input  rstn;

input  load;                                    // load enable displaying data
input  disable_en;                              // disable_en state displaying "--.--"
input  [3:0]  bcd0;
input  [3:0]  bcd1;
input  [3:0]  bcd2;
input  [3:0]  bcd3;

input  dp0;
input  dp1;
input  dp2;
input  dp3;

input  seg_en0;
input  seg_en1;
input  seg_en2;
input  seg_en3;

`ifdef DEBUG
output TestTP0_T;                           // Test IO uesd to Test Signal in FPGA PCB Board Level,Not in Function Simulation.
`endif

output [3:0]  seg7_bit;
output [7:0]  seg7_led;

/********************* VARIABLE DECLARATION ********************/
`ifdef DEBUG
wire TestTP0_T;
`endif

wire   [3:0] seg_en;
//wire clk_slow;
//---------------------------------------------------------
reg    [1:0]  sel;
reg    [3:0]  bcd_led;
reg    dp;
//reg    [15:0] clk_cnt;
//OUTPUT
reg    [3:0]  seg7_bit;
reg    [7:0]  seg7_led;
//===================================================================
//                            Test Process
//===================================================================


//===================================================================
//                             Clock Setup
//===================================================================
/*always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    clk_cnt <= 16'b0;
  else
    clk_cnt <= clk_cnt + 16'b1;
end

assign clk_slow = clk_cnt[15];*/

//===================================================================
//                             bit select
//===================================================================
assign seg_en = {seg_en3,seg_en2,seg_en1,seg_en0};

always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    sel <= 2'b00;
  else
    sel <= sel + 2'b01;
end

//===================================================================
//                   BCD code MUX and Latch Register
//===================================================================
always @(sel or bcd0 or bcd1 or bcd2 or bcd3)
begin
  case(sel)
    2'b00:   bcd_led = bcd0;
    2'b01:   bcd_led = bcd1;
    2'b10:   bcd_led = bcd2;
    2'b11:   bcd_led = bcd3;
    default: bcd_led = 4'b0000;     //has any extra logic?
  endcase
end

always @(sel or dp0 or dp1 or dp2 or dp3)
begin
  case(sel)
    2'b00:   dp = dp0;
    2'b01:   dp = dp1;
    2'b10:   dp = dp2;
    2'b11:   dp = dp3;
    default: dp = 1'b0;
  endcase
end

always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    seg7_bit <= 4'b0000;
  else// if(load)                              //bcd:       bcd3   bcd2   bcd1   bcd0
    case(sel)                                   //sel:        00     01     10     11
      2'b00:   seg7_bit <= 4'b0001 & seg_en;    //            --     --     --     --
      2'b01:   seg7_bit <= 4'b0010 & seg_en;    //           |  |   |  |   |  |   |  |
      2'b10:   seg7_bit <= 4'b0100 & seg_en;    //            --     --     --     --
      2'b11:   seg7_bit <= 4'b1000 & seg_en;    //           |  |   |  |   |  |   |  |
      default: seg7_bit <= 4'b0000;             //            -- .   -- .   -- .   -- .
    endcase                                     //seg7_bit:  1000   0100   0010   0001
end

//===================================================================
//                             LED decoder
//===================================================================
always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    seg7_led <= 8'b0000_0000;
  else if(load)
    if(disable_en)
      seg7_led <= {7'b0000_001,dp};             // invalid state."--.--"
    else
      case(bcd_led)
        4'h0:    seg7_led <= {7'b1111_110,dp};  // seg7_led[7:0](high active)-------
        4'h1:    seg7_led <= {7'b0110_000,dp};  // a,b,c,d,e,f,g,dp
        4'h2:    seg7_led <= {7'b1101_101,dp};  //
        4'h3:    seg7_led <= {7'b1111_001,dp};  //      -a-
        4'h4:    seg7_led <= {7'b0110_011,dp};  //    f|   |b
        4'h5:    seg7_led <= {7'b1011_011,dp};  //      -g-
        4'h6:    seg7_led <= {7'b1011_111,dp};  //    e|   |c
        4'h7:    seg7_led <= {7'b1110_000,dp};  //      -d- .dp
        4'h8:    seg7_led <= {7'b1111_111,dp};  //----------------------------------
        4'h9:    seg7_led <= {7'b1111_011,dp};
        4'ha:    seg7_led <= {7'b1110_111,dp};
        4'hb:    seg7_led <= {7'b0011_111,dp};
        4'hc:    seg7_led <= {7'b1001_110,dp};
        4'hd:    seg7_led <= {7'b0111_101,dp};
        4'he:    seg7_led <= {7'b1001_111,dp};
        4'hf:    seg7_led <= {7'b1000_111,dp};
        default: seg7_led <= {7'b0000_000,dp};
      endcase
end

endmodule