speaker.v

自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,

module SPEAKER(
// CLOCK & RESET
       clk_6mhz,
       clk_4hz,
       rstn,
// INPUT
       en,
// OUTPUT
       sp
);

/******************* PARAMETER DECLARATION *********************/

/*********************** IO DECLARATION ************************/
//TEST

//INPUT
input clk_6mhz,clk_4hz;
input rstn;
input en;

//OUTPUT
output sp;
/********************* VARIABLE DECLARATION ********************/
wire carry;
//----------------------------------------------------
reg [13:0] divider,origin;
reg [7:0] counter;
reg sp;
reg [3:0] high,med,low;
reg en_syn6MHz,en_syn4Hz;
/**************************** MAIN *****************************/
//===============================================================
//                            TEST
//===============================================================


//===============================================================
//                         Preload Divider
//===============================================================
always @(posedge clk_6mhz or negedge rstn)
begin
  if(!rstn)
    en_syn6MHz <= 1'b0;
  else
    en_syn6MHz <= en;
end

assign carry = (divider == 16383);

always @(posedge clk_6mhz or negedge rstn)
begin
  if(!rstn)
    divider <= 14'b0;
  else if(en_syn6MHz)
    if(carry)
      divider <= origin;
    else
      divider <= divider + 1;
  else
    divider <= 14'b0;
end

//===============================================================
//                         Sounds Decoder
//===============================================================
always@(posedge clk_4hz or negedge rstn)
begin
  if(!rstn)
    origin <= 14'b0;
  else
    case({high,med,low})
    'b000000000011:   origin <= 7281;
    'b000000000101:   origin <= 8730;
    'b000000000110:   origin <= 9565;
    'b000000000111:   origin <= 10310;
    'b000000010000:   origin <= 10647;
    'b000000100000:   origin <= 11272;
    'b000000110000:   origin <= 11831;
    'b000001010000:   origin <= 12556;
    'b000001100000:   origin <= 12974;
    'b000100000000:   origin <= 13516;
    'b000000000000:   origin <= 16383;
    endcase
end

always @(posedge clk_4hz or negedge rstn)
begin
  if(!rstn)
    en_syn4Hz <= 1'b0;
  else
    en_syn4Hz <= en;
end

always @(posedge clk_4hz or negedge rstn)
begin
  if(!rstn)
    counter <= 0;
  else if(en_syn4Hz)
    if(counter==50)
      counter <= 0;
    else
      counter <= counter + 1;
  else
    counter <= 0;
end

always @(posedge clk_4hz or negedge rstn)
begin
  if(!rstn)
    {high,med,low} <= 'b0;
  else
    case(counter)
     0:  {high,med,low}<='b000000000011;
     1:  {high,med,low}<='b000000000011; 
     2:  {high,med,low}<='b000000000011;   
     3:  {high,med,low}<='b000000000011;
     4:  {high,med,low}<='b000000000101;
     5:  {high,med,low}<='b000000000101;
     6:  {high,med,low}<='b000000000101;
     7:  {high,med,low}<='b000000000110;
     8:  {high,med,low}<='b000000010000;
     9:  {high,med,low}<='b000000010000;
    10:  {high,med,low}<='b000000010000;
    11:  {high,med,low}<='b000000100000;
    12:  {high,med,low}<='b000000000110;
    13:  {high,med,low}<='b000000010000;
    14:  {high,med,low}<='b000000000101;
    15:  {high,med,low}<='b000000000101; 
     
    16:  {high,med,low}<='b000001010000; 
    17:  {high,med,low}<='b000001010000;   
    18:  {high,med,low}<='b000001010000;
    19:  {high,med,low}<='b000100000000;
    20:  {high,med,low}<='b000001100000;
    21:  {high,med,low}<='b000001010000;
    22:  {high,med,low}<='b000000110000;
    23:  {high,med,low}<='b000001010000;
    24:  {high,med,low}<='b000000100000;
    25:  {high,med,low}<='b000000100000;
    26:  {high,med,low}<='b000000100000;
    27:  {high,med,low}<='b000000100000;
    28:  {high,med,low}<='b000000100000;
    29:  {high,med,low}<='b000000100000;
    30:  {high,med,low}<='b000000100000;     
    31:  {high,med,low}<='b000000100000; 
    
    
    32:  {high,med,low}<='b000000100000;   
    33:  {high,med,low}<='b000000100000;
    34:  {high,med,low}<='b000000100000;
    35:  {high,med,low}<='b000000110000;
    36:  {high,med,low}<='b000000000111;
    37:  {high,med,low}<='b000000000111;
    38:  {high,med,low}<='b000000000110;
    39:  {high,med,low}<='b000000000110;
    40:  {high,med,low}<='b000000000101;
    41:  {high,med,low}<='b000000000101;
    42:  {high,med,low}<='b000000000101;
    43:  {high,med,low}<='b000000000110;
    44:  {high,med,low}<='b000000010000;
    45:  {high,med,low}<='b000000010000;
    46:  {high,med,low}<='b000000100000;
    47:  {high,med,low}<='b000000100000;
    default:{high,med,low}<='d0;
    endcase
end

//===============================================================
//                        Output to Speaker
//===============================================================
always@(posedge clk_6mhz or negedge rstn)
begin
  if(!rstn)
    sp <= 1'b0;
  else if(en_syn6MHz && carry)
    sp <= ~sp;
  //else if(!en_syn6MHz)
    //sp <= 1'b0;
end

endmodule