digit_clock_top.v

自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,

module DIGIT_CLOCK_TOP(
//CLOCK & RESET
       clk_in,
       //clk_1k,
       //clk_8Hz,
       //clk_1Hz,
       rst_n,
//INPUT
       KEY_MODE,
       KEY_SET,
       KEY_DOWN,
       KEY_UP,
//OUTPUT
       SEG_LED_S0,
       SEG_LED_S1,
       SEG_LED_S2,
       SEG_LED_S3,
       data0,
       data1,
       data2,
       data3,
       data4,
       data5,
       data6,
       data7,
       alert
);

/******************* PARAMETER DECLARATION *********************/
parameter KEYDLYSEC = 5;                        // keep the key pressing down for 5 seconds.
parameter KEYDLY1S_CKS = 8;                     // clock frequency is 8Hz.
/*********************** IO DECLARATION ************************/
input clk_in;
//input clk_1k,clk_8Hz,clk_1Hz;
input rst_n;
input KEY_MODE,KEY_SET,KEY_DOWN,KEY_UP;

output SEG_LED_S0,SEG_LED_S1,SEG_LED_S2,SEG_LED_S3;
output data0,data1,data2,data3;
output data4,data5,data6,data7;
output alert;                                   // Speaker.

/********************* VARIABLE DECLARATION ********************/
reg [23:0] clk_cnt;
reg mode;                                       // function select signal.mode=0,timing;mode=1,alarm clock.
reg [7:0] setsec,setmin,sethour;                // set time count of second,minite,hour.
//reg [7:0] tsec,tmin,thour;                      // timing second,minite,hour count to display.
reg [7:0] amin,ahour;                           // alarm count of minite,hour.
reg [4:0] keyset_cnt;
reg alarm_valid;
reg set_time_str;                               // set time start signal.
reg set_alarm_str;                              // set alarm start signal.
reg [1:0] set_time_state;
reg [1:0] set_alarm_state;
reg min_en,hour_en;

reg up_slow,down_slow;
reg up_fast,down_fast;
reg [2:0] keyup_slowcnt,keyup_fastcnt;
reg [2:0] keydown_slowcnt,keydown_fastcnt;
reg [2:0] t1s_count;

reg alarm_en;
reg key_disable;

wire clk_8Hz,clk_8Hzbuf;
wire clk_1k,clk_1kbuf;
wire clk_1Hz,clk_1Hzbuf;
wire clk_6mhz,clk_4hz;

wire km;                                        // mode key pulse.
wire ks;                                        // set key pulse.
wire ks_l;                                      // set key long.
wire key_downp;                                 // down key pulse.
wire key_downl;                                 // down key long.
wire key_upp;                                   // up key pulse.
wire key_upl;                                   // up key long.
wire disalarm0,disalarm1;                       // disable alarm.

wire up_en,down_en;

wire [3:0] cnt0,cnt1,cnt2,cnt3;
//===================================================================
//                           Clock Process
//===================================================================
CLK_GEN CLK_GEN(
    .clk_50MHz(clk_in),
    .rst_al(rst_n),
    .clk_1k(clk_1kbuf),
    .clk_8Hz(clk_8Hzbuf),
    .clk_1Hz(clk_1Hzbuf)
);

BUFG clk_buf1(.O(clk_1k),.I(clk_1kbuf));
BUFG clk_buf2(.O(clk_8Hz),.I(clk_8Hzbuf));
BUFG clk_buf3(.O(clk_1Hz),.I(clk_1Hzbuf));

//===================================================================
//                             Key Process
//===================================================================
KEY_USE KEYMODE(
    .clk_cp(clk_8Hz),
    .rst_al(rst_n),
    .pb_in(KEY_MODE),
    .pb_up(),
    .pb_down(km),
    .pb_out()
);

KEY_USE KEYSET(
    .clk_cp(clk_8Hz),
    .rst_al(rst_n),
    .pb_in(KEY_SET),
    .pb_up(ks),
    .pb_down(),
    .pb_out(ks_l)
);

KEY_USE KEYDOWN(
    .clk_cp(clk_8Hz),
    .rst_al(rst_n),
    .pb_in(KEY_DOWN),
    .pb_up(key_downp),
    .pb_down(disalarm0),
    .pb_out(key_downl)
);

KEY_USE KEYUP(
    .clk_cp(clk_8Hz),
    .rst_al(rst_n),
    .pb_in(KEY_UP),
    .pb_up(key_upp),
    .pb_down(disalarm1),
    .pb_out(key_upl)
);

//set key
always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    keyset_cnt <= 5'b00000;
  else if(!ks_l)
    if(keyset_cnt==5'd25)
      keyset_cnt <= keyset_cnt;
    else
      keyset_cnt <= keyset_cnt + 1;
  else
    keyset_cnt <= 5'b00000;
end

always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    alarm_valid <= 1'b0;
  else if(mode && keyset_cnt==5'd24)          // in alarm mode.
    alarm_valid <= ~ alarm_valid;             // alarm on or off,alarm_valid=0 is alarm off.
  else
    alarm_valid <= alarm_valid;
end

//===================================================================
//                      Data Control(Controller)
//===================================================================
//control flow
always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    mode <= 1'b0;
  else if(km)
    mode <= ~ mode;                             // mode = 0:time,1:alarm
end

always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
  begin
    set_time_str <= 1'b0;
    set_alarm_str <= 1'b0;
  end
  else if(mode)
  begin
    set_time_str <= 1'b0;
    set_alarm_str <= ks;
  end
  else
  begin
    set_time_str <= ks;
    set_alarm_str <= 1'b0;
  end
end

always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    set_time_state <= 2'b00;
  else if(!mode)
    if(set_time_state==2'b10 && set_time_str)
      set_time_state <= 2'b00;                  // set_time_state = 0:hour&min on,1:hour flash,2:min flash.
    else if(set_time_str)
      set_time_state <= set_time_state + 1;
    else
      set_time_state <= set_time_state;
  else
    set_time_state <= 2'b00;
end

always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    set_alarm_state <= 2'b00;
  else if(mode && alarm_valid)                  //闹钟关闭时(alarm_valid=0)禁止set_alarm_state状态转换
    if((set_alarm_state==2'b10||keyset_cnt==5'd25)&& set_alarm_str)//禁止闹钟打开或关闭(alarm_valid)切换时的set_alarm_state转换
      set_alarm_state <= 2'b00;
    else if(set_alarm_str)
      set_alarm_state <= set_alarm_state + 1;
    else
      set_alarm_state <= set_alarm_state;
  else
    set_alarm_state <= 2'b00;
end

always @(set_time_state or set_alarm_state or alarm_valid or rst_n or mode or clk_1Hz)
begin
  if(!rst_n)
  begin
    min_en  = 1'b0;
    hour_en = 1'b0;
  end
  else if(!mode)
    case(set_time_state)
      2'b00:
      begin
        min_en  = 1'b1;
        hour_en = 1'b1;
      end
      2'b01:
      begin
        min_en  = clk_1Hz;
        hour_en = 1'b1;
      end
      2'b10:
      begin
        min_en  = 1'b1;
        hour_en = clk_1Hz;
      end
      default:
      begin
        min_en  = 1'b1;
        hour_en = 1'b1;
      end
    endcase
  else if(alarm_valid)                          // it is valid that min/hour flash in set alarm state when alarm on.
    case(set_alarm_state)
      2'b00:
      begin
        min_en  = 1'b1;
        hour_en = 1'b1;
      end
      2'b01:
      begin
        min_en  = clk_1Hz;
        hour_en = 1'b1;
      end
      2'b10:
      begin
        min_en  = 1'b1;
        hour_en = clk_1Hz;
      end
      default:
      begin
        min_en  = 1'b1;
        hour_en = 1'b1;
      end
    endcase
  else
  begin
    min_en  = 1'b1;
    hour_en = 1'b1;
  end
end

//up key
always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
  begin
    up_slow <= 1'b0;
    keyup_slowcnt <= 3'b000;
    keyup_fastcnt <= 3'b000;
  end
  else if(!key_upl)
  begin
    keyup_slowcnt <= keyup_slowcnt + 1;
    if(keyup_slowcnt==KEYDLY1S_CKS-1 && keyup_fastcnt==0)
    begin
      up_slow <= 1'b0;                          // no action at up key press 1st second.
      keyup_fastcnt <= keyup_fastcnt + 1;
    end
    else if(keyup_slowcnt==KEYDLY1S_CKS-1)
    begin
      up_slow <= 1'b1;
      keyup_fastcnt <= keyup_fastcnt + 1;
    end
    else
    begin
      up_slow <= 1'b0;
      keyup_fastcnt <= keyup_fastcnt;
    end
  end
  else
  begin
    up_slow <= 1'b0;
    keyup_slowcnt <= 3'b000;
    keyup_fastcnt <= 3'b000;
  end
end

always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
    up_fast <= 1'b0;
  else if(keyup_fastcnt==KEYDLYSEC)
    up_fast <= 1'b1;
  else if(key_upp)
    up_fast <= 1'b0;
end

assign up_en = up_slow || up_fast || key_upp;   // key_upp ensure to press key 1 time.

//---------------------------------------------------------
//down key
always @(posedge clk_8Hz or negedge rst_n)
begin
  if(!rst_n)
  begin
    down_slow <= 1'b0;
    keydown_slowcnt <= 3'b000;
    keydown_fastcnt <= 3'b000;
  end
  else if(!key_downl)