clk_gen.v

自己写的数字闹钟含校时和闹钟设定,闹钟铃声为梁柱歌曲,

//`define DEBUG
module CLK_GEN(
// TEST
       `ifdef DEBUG
       TestTP0_T,
       `endif

// INPUT
       clk_50MHz,
       rst_al,
       
// OUTPUT
       clk_1k,
       clk_8Hz,
       clk_1Hz
       );

/******************* PARAMETER DECLARATION *********************/


/*********************** IO DECLARATION ************************/
input clk_50MHz;                            // System Reference Clock Input.
input rst_al;                               // Asynchronous Reference Reset.

`ifdef DEBUG
output TestTP0_T;                           // Test IO uesd to Test Signal in FPGA PCB Board Level,Not in Function Simulation.
`endif

output clk_8Hz;
reg    clk_8Hz;
output clk_1Hz;
reg    clk_1Hz;
output clk_1k;
reg    clk_1k;
/********************* VARIABLE DECLARATION ********************/
`ifdef DEBUG
wire TestTP0_T;
`endif

//----------------------------------------------------------
reg [5:0] div1_cnt;
reg [8:0] div2_cnt;
reg [6:0] div3_cnt;
reg [2:0] div4_cnt;

reg div1_carry;
reg div2_carry;
reg div3_carry;
reg div4_carry;

//===================================================================
//                            Test Process
//===================================================================
`ifdef DEBUG
assign TestTP0_T = clk_1Hz;
`endif

//===================================================================
//                         Generate 1Hz Clock
//===================================================================
always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
  begin
    div1_cnt <= 0;
    div1_carry <= 0;
  end
  else
  begin
    if(div1_cnt == 6'd49)                       // 50MHz / ((div1_cnt+1) = 1MHz.
    begin
      div1_cnt <= 0;
      div1_carry <= 1;
    end
    else
    begin
      div1_cnt <= div1_cnt + 1;
      div1_carry <= 0;
    end
  end
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
  begin
    div2_cnt <= 0;
    div2_carry <= 0;
  end
  else
  begin
    if((div2_cnt == 9'd499)&&div1_carry)        // 1MHz / ((div2_cnt+1) = 2KHz.
    begin
      div2_cnt <= 0;
      div2_carry <= 1;
    end
    else if(div1_carry)
    begin
      div2_cnt <= div2_cnt + 1;
      div2_carry <= 0;
    end
    else
      div2_carry <= 0;
  end
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
  begin
    div3_cnt <= 0;
    div3_carry <= 0;
  end
  else
  begin
    if((div3_cnt == 7'd124)&&div2_carry)        // 2KHz / ((div3_cnt+1) = 16Hz.
    begin
      div3_cnt <= 0;
      div3_carry <= 1;
    end
    else if(div2_carry)
    begin
      div3_cnt <= div3_cnt + 1;
      div3_carry <= 0;
    end
    else
      div3_carry <= 0;
  end
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
  begin
    div4_cnt <= 0;
    div4_carry <= 0;
  end
  else
  begin
    if((div4_cnt == 3'd7)&&div3_carry)          // 16Hz / ((div4_cnt+1) = 2Hz.
    begin
      div4_cnt <= 0;
      div4_carry <= 1;
    end
    else if(div3_carry)
    begin
      div4_cnt <= div4_cnt + 1;
      div4_carry <= 0;
    end
    else
      div4_carry <= 0;
  end
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
    clk_1k <= 1'b0;
  else if(div2_carry)
    clk_1k <= ~ clk_1k;                         // 2KHz / 2 = 1KHz.
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
    clk_8Hz <= 0;
  else if(div3_carry)
    clk_8Hz <= ~ clk_8Hz;                       // 16Hz / 2 = 8Hz.
end

always @(posedge clk_50MHz or negedge rst_al)
begin
  if(!rst_al)
    clk_1Hz <= 0;
  else if(div4_carry)
    clk_1Hz <= ~ clk_1Hz;                       // 2Hz / 2 = 1Hz.
end

endmodule