sam9260.s

开发板AT91SAM9260-EK的测试程序

;//                   <i> broken by another master trying to access this slave
;//       <o3.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o3.18..20> FIXED_DEFMSTR: Fixed Index of Default Master <0-7>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o3.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//     <h> Bus Master Slave Configuration Regsiter 4 (MATRIX_SCFG4)
;//       <o4.0..7>   SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;//                   <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;//                   <i> broken by another master trying to access this slave
;//       <o4.16..17> DEFMASTR_TYPE: Default Master Type
;//                   <0=> No Default Master
;//                   <1=> Last Default Master
;//                   <2=> Fixed Default Master
;//       <o4.18..20> FIXED_DEFMSTR: Fixed Index of Default Master <0-7>
;//                   <i> This is the index of the Fixed Default Master for this slave
;//       <o4.24..25> ARBT: Arbitration Type
;//                   <0=> Round-Robin Arbitration
;//                   <1=> Fixed Priority Arbitration
;//     </h>
;//   </h>
MATRIX_SCFG0_Val EQU    0x00000010
MATRIX_SCFG1_Val EQU    0x00000010
MATRIX_SCFG2_Val EQU    0x00000010
MATRIX_SCFG3_Val EQU    0x00000010
MATRIX_SCFG4_Val EQU    0x00000010

;//   <h> Bus Matrix Priority Registers For Slaves
;//     <h> Bus Matrix Priority Registers For Slaves 0 (MATRIX_PRAS0)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//     </h>
;//     <h> Bus Matrix Priority Registers For Slaves 1 (MATRIX_PRAS1)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//     </h>
;//     <h> Bus Matrix Priority Registers For Slaves 2 (MATRIX_PRAS2)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//     </h>
;//     <h> Bus Matrix Priority Registers For Slaves 3 (MATRIX_PRAS3)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//     </h>
;//     <h> Bus Matrix Priority Registers For Slaves 4 (MATRIX_PRAS4)
;//       <i> Fixed priority of Master x for access to the selected slave.
;//       <i> The higher the number, the higher the priority.
;//       <o0.0..1>   M0PR: Master 0 Priority
;//       <o0.4..5>   M1PR: Master 1 Priority
;//       <o0.8..9>   M2PR: Master 2 Priority
;//       <o0.12..13> M3PR: Master 3 Priority
;//       <o0.16..17> M4PR: Master 4 Priority
;//       <o0.20..21> M5PR: Master 5 Priority
;//     </h>
;//   </h>
MATRIX_PRAS0_Val EQU    0x00000000
MATRIX_PRAS1_Val EQU    0x00000000
MATRIX_PRAS2_Val EQU    0x00000000
MATRIX_PRAS3_Val EQU    0x00000000
MATRIX_PRAS4_Val EQU    0x00000000

;// </e> Bus Matrix (MATRIX)


;// <e> External Bus Interface (EBI)
EBI_SETUP       EQU     1

;//   <h> EBI Chip Select Assignment Register
;//     <o0.1>      EBI_CS1A: EBI Chip Select 1 Assignment
;//                   <0=> Assigned to Static Memory Controller
;//                   <1=> Assigned to SDRAM Controller
;//     <o0.3>      EBI_CS3A: EBI Chip Select 3 Assignment
;//                   <0=> Assigned to Static Memory Controller
;//                   <1=> Assigned to Static Memory Controller and the SmartMedia Logic
;//     <o0.4>      EBI_CS4A: EBI Chip Select 4 Assignment
;//                   <0=> Assigned to Static Memory Controller
;//                   <1=> Assigned to Static Memory Controller and the CompactFlash Logic (Slot 1)
;//     <o0.5>      EBI_CS5A: EBI Chip Select 5 Assignment
;//                   <0=> Assigned to Static Memory Controller
;//                   <1=> Assigned to Static Memory Controller and the CompactFlash Logic (Slot 2)
;//     <o0.8>      EBI_DBPUC: EBI Data Bus Pull-UP Configuration
;//                   <0=> EBI D0..D15 Data Bus bits are internally pulled-up
;//                   <1=> EBI D0..D15 Data Bus bits are not internally pulled-up
;//     <o0.16>     VDDIOMSEL: Memory Voltage Selection
;//                   <0=> Memories are 1.8V powered
;//                   <1=> Memories are 3.3V powered
;//   </h>
EBI_CSA_Val     EQU     0x0001003A

;// </e> External Bus Interface (EBI)


;----------------------- Static Memory Controller (SMC) Definitions ------------

; Static Memory Controller (SMC) User Interface
SMC_BASE        EQU     0xFFFFEC00      ; SMC                     Base Address

                ^       0               ; SMC Registers           Offsets
SMC_SETUP0_OFS  #       0x04            ; CS0 Setup Register      Address Offset
SMC_PULSE0_OFS  #       0x04            ; CS0 Pulse Register      Address Offset
SMC_CYCLE0_OFS  #       0x04            ; CS0 Cycle Register      Address Offset
SMC_MODE0_OFS   #       0x04            ; CS0 Mode  Register      Address Offset

SMC_SETUP1_OFS  #       0x04            ; CS1 Setup Register      Address Offset
SMC_PULSE1_OFS  #       0x04            ; CS1 Pulse Register      Address Offset
SMC_CYCLE1_OFS  #       0x04            ; CS1 Cycle Register      Address Offset
SMC_MODE1_OFS   #       0x04            ; CS1 Mode  Register      Address Offset

SMC_SETUP2_OFS  #       0x04            ; CS2 Setup Register      Address Offset
SMC_PULSE2_OFS  #       0x04            ; CS2 Pulse Register      Address Offset
SMC_CYCLE2_OFS  #       0x04            ; CS2 Cycle Register      Address Offset
SMC_MODE2_OFS   #       0x04            ; CS2 Mode  Register      Address Offset

SMC_SETUP3_OFS  #       0x04            ; CS3 Setup Register      Address Offset
SMC_PULSE3_OFS  #       0x04            ; CS3 Pulse Register      Address Offset
SMC_CYCLE3_OFS  #       0x04            ; CS3 Cycle Register      Address Offset
SMC_MODE3_OFS   #       0x04            ; CS3 Mode  Register      Address Offset

SMC_SETUP4_OFS  #       0x04            ; CS4 Setup Register      Address Offset
SMC_PULSE4_OFS  #       0x04            ; CS4 Pulse Register      Address Offset
SMC_CYCLE4_OFS  #       0x04            ; CS4 Cycle Register      Address Offset
SMC_MODE4_OFS   #       0x04            ; CS4 Mode  Register      Address Offset

SMC_SETUP5_OFS  #       0x04            ; CS5 Setup Register      Address Offset
SMC_PULSE5_OFS  #       0x04            ; CS5 Pulse Register      Address Offset
SMC_CYCLE5_OFS  #       0x04            ; CS5 Cycle Register      Address Offset
SMC_MODE5_OFS   #       0x04            ; CS5 Mode  Register      Address Offset

SMC_SETUP6_OFS  #       0x04            ; CS6 Setup Register      Address Offset
SMC_PULSE6_OFS  #       0x04            ; CS6 Pulse Register      Address Offset
SMC_CYCLE6_OFS  #       0x04            ; CS6 Cycle Register      Address Offset
SMC_MODE6_OFS   #       0x04            ; CS6 Mode  Register      Address Offset

SMC_SETUP7_OFS  #       0x04            ; CS7 Setup Register      Address Offset
SMC_PULSE7_OFS  #       0x04            ; CS7 Pulse Register      Address Offset
SMC_CYCLE7_OFS  #       0x04            ; CS7 Cycle Register      Address Offset
SMC_MODE7_OFS   #       0x04            ; CS7 Mode  Register      Address Offset

;// <e> Static Memory Controller (SMC)
SMC_SETUP       EQU     0

;//   <e> SMC Chip Select 0 Configuration
;//     <h> Chip Select 0 Setup Register (SMC_SETUP0)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 0 Pulse Register (SMC_PULSE0)
;//       <o2.0..6>   NWE_PULSE: NWE Pulse Length <0-63>
;//                     <i> NWE pulse length = (128*NWE_PULSE[6]+NWE_PULSE[5..0]) clock cycles
;//       <o2.8..14>  NCS_WR_PULSE: NCS Pulse Length in WRITE Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_WR_PULSE[6]+NCS_WR_PULSE[5..0]) clock cycles
;//       <o2.16..22> NRD_PULSE: NRD Pulse Length <0-63>
;//                     <i> NRD pulse length = (128*NRD_PULSE[6]+NRD_PULSE[5..0]) clock cycles
;//       <o2.24..30> NCS_RD_PULSE: NCS Pulse Length in READ Access <0-63>
;//                     <i> NCS pulse length = (128*NCS_RD_PULSE[6]+NCS_RD_PULSE[5..0]) clock cycles
;//     </h>
;//
;//     <h> Chip Select 0 Cycle Register (SMC_CYCLE0)
;//       <o3.0..8>   NWE_CYCLE: Total Write Cycle Length <0-511>
;//                     <i> Write cycle length = (NWE_CYCLE[8..7]*256+NWE_CYCLE[6..0]) clock cycle
;//       <o3.16..24> NRD_CYCLE: Total Read Cycle Length <0-511>
;//                     <i> Read cycle length = (NRD_CYCLE[8..7]*256+NRD_CYCLE[6..0]) clock cycle
;//     </h>
;//
;//     <h> Chip Select 0 Mode Register (SMC_MODE0)
;//       <o4.0>      READ_MODE:
;//                     <0=> The read operation is controlled by the NCS signal
;//                     <1=> The read operation is controlled by the NRD signal
;//       <o4.1>      WRITE_MODE:
;//                     <0=> The write operation is controlled by the NCS signal
;//                     <1=> The write operation is controlled by the NWE signal
;//       <o4.4..5>   EXNW_MODE: NWAIT Mode
;//                     <0=> Disabled
;//                     <2=> Frozen Mode
;//                     <3=> Ready Mode
;//       <o4.8>      BAT: Byte Access Type
;//                     <0=> 0
;//                     <1=> 1
;//                     <i>  0: - Write operation is controlled using: NCS, NWE, NBS0, NBS1, NBS2, NBS3
;//                     <i>     - Read  operation is controlled using: NCS, NRD, NBS0, NBS1, NBS2, NBS3
;//                     <i>  1: - Write operation is controlled using: NCS, NWR0, NWR1, NWR2, NWR3        
;//                     <i>     - Read  operation is controlled using: NCS, NRD
;//       <o4.12..13> DBW: Data Bus Width
;//                     <0=> 8-bit bus
;//                     <1=> 16-bit bus
;//                     <2=> 32-bit bus
;//       <o4.16..19> TDF_CYCLES: Data Float Time <0-15>
;//       <o4.20>     TDF_MODE: TDF Optimization Enabled
;//       <o4.24>     PMEN: Page Mode Enabled
;//       <o4.28..29> PS: Page Size
;//                     <0=> 4-byte page
;//                     <1=> 8-byte page
;//                     <2=> 16-byte page
;//                     <3=> 32-byte page
;//     </h>
;//   </e>
SMC_CS0_SETUP   EQU     0x00000000
SMC_SETUP0_Val  EQU     0x00000000
SMC_PULSE0_Val  EQU     0x01010101
SMC_CYCLE0_Val  EQU     0x00010001
SMC_MODE0_Val   EQU     0x10001000

;//   <e> SMC Chip Select 1 Configuration
;//     <h> Chip Select 1 Setup Register (SMC_SETUP1)
;//       <o1.0..5>   NWE_SETUP: NWE Setup Length <0-31>
;//                     <i> NWE setup length = (128*NWE_SETUP[5]+NWE_SETUP[4..0]) clock cycles
;//       <o1.8..13>  NCS_WR_SETUP: NCS Setup Length in WRITE Access <0-31>
;//                     <i> NCS setup length = (128*NCS_WR_SETUP[5]+NCS_WR_SETUP[4..0]) clock cycles
;//       <o1.16..21> NRD_SETUP: NRD Setup Length <0-31>
;//                     <i> NRD setup length = (128*NRD_SETUP[5]+NRD_SETUP[4..0]) clock cycles
;//       <o1.24..29> NCS_RD_SETUP: NCS Setup Length in READ Access <0-31>
;//                     <i> NCS setup length = (128*NCS_RD_SETUP[5]+NCS_RD_SETUP[4..0]) clock cycles