📄 sam9260.s
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;/*****************************************************************************/
;/* SAM9260.S: Startup file for Atmel AT91SAM9260 device series */
;/*****************************************************************************/
;/* <<< Use Configuration Wizard in Context Menu >>> */
;/*****************************************************************************/
;/* This file is part of the uVision/ARM development tools. */
;/* Copyright (c) 2005-2007 Keil Software. All rights reserved. */
;/* This software may only be used under the terms of a valid, current, */
;/* end user licence from KEIL for a compatible version of KEIL software */
;/* development tools. Nothing else gives you the right to use this software. */
;/*****************************************************************************/
;/*
; * The SAM9260.S code is executed after CPU Reset. This file may be
; * translated with the following SET symbols. In uVision these SET
; * symbols are entered under Options - ASM - Define.
; *
; * SIZE_INFO: size of program image is coded instead of Reserved vector
; * at address 0x14.
; *
; * REMAP: when set the startup code remaps exception vectors from
; * on-chip RAM to address 0.
; *
; * RAM_INTVEC: when set the startup code copies exception vectors
; * from on-chip Flash to on-chip RAM.
; *
; * NO_SDRAM_INIT: when set the SDRAM controller is not initialized in startup
; * and it is used when SDRAM controller is initialized from debugger
; * enviroment (using the debug script).
; *
; * NO_PMC_INIT: when set the Power Management Controller and system clock
; * are not initialized in startup and it is used when PLL is initialized from
; * debugger enviroment (using the debug script).
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
; Internal Memory Base Addresses
IRAM_BASE EQU 0x00200000
IROM_BASE EQU 0x00100000
;// <h> Stack Configuration (Stack Sizes in Bytes)
;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
;// </h>
UND_Stack_Size EQU 0x00000000
SVC_Stack_Size EQU 0x00000008
ABT_Stack_Size EQU 0x00000000
FIQ_Stack_Size EQU 0x00000000
IRQ_Stack_Size EQU 0x00000080
USR_Stack_Size EQU 0x00000400
Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
FIQ_Stack_Size + IRQ_Stack_Size + USR_Stack_Size)
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
Stack_Top EQU Stack_Mem + Stack_Size
;// <h> Heap Configuration
;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
;// </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
Heap_Mem SPACE Heap_Size
;----------------------- PIOs Definitions --------------------------------------
; Parallel Input/Output Controller (PIO) User Interface
PIOA_BASE EQU 0xFFFFF400 ; PIO A Base Address
PIOB_BASE EQU 0xFFFFF600 ; PIO B Base Address
PIOC_BASE EQU 0xFFFFF800 ; PIO C Base Address
PIO_PER_OFS EQU 0x00 ; PIO Enable Register Address Offset
PIO_PDR_OFS EQU 0x04 ; PIO Disable Register Address Offset
PIO_OER_OFS EQU 0x10 ; PIO Output Enable Reg Address Offset
PIO_ODR_OFS EQU 0x14 ; PIO Output Disable Reg Address Offset
PIO_MDER_OFS EQU 0x50 ; PIO Multi-Driver En Reg Address Offset
PIO_MDDR_OFS EQU 0x54 ; PIO Multi-Driver Ds Reg Address Offset
PIO_PUDR_OFS EQU 0x60 ; PIO Pull-up Disable Reg Address Offset
PIO_PUER_OFS EQU 0x64 ; PIO Pull-up Enable Reg Address Offset
PIO_ASR_OFS EQU 0x70 ; PIO Periph A Select Reg Address Offset
PIO_BSR_OFS EQU 0x74 ; PIO Periph B Select Reg Address Offset
;----------------------- MATRIX Definitions ------------------------------------
; Bus Matrix (MATRIX) User Interface
; |- External Bus Interface (EBI) User Interface
MATRIX_BASE EQU 0xFFFFEE00 ; Bus Matrix Base Address
MATRIX_MCFG0_OFS EQU 0x00 ; Master Config Reg 0 Address Offset
MATRIX_MCFG1_OFS EQU 0x04 ; Master Config Reg 1 Address Offset
MATRIX_MCFG2_OFS EQU 0x08 ; Master Config Reg 2 Address Offset
MATRIX_MCFG3_OFS EQU 0x0C ; Master Config Reg 3 Address Offset
MATRIX_MCFG4_OFS EQU 0x10 ; Master Config Reg 4 Address Offset
MATRIX_MCFG5_OFS EQU 0x14 ; Master Config Reg 5 Address Offset
MATRIX_SCFG0_OFS EQU 0x40 ; Slave Config Reg 0 Address Offset
MATRIX_SCFG1_OFS EQU 0x44 ; Slave Config Reg 1 Address Offset
MATRIX_SCFG2_OFS EQU 0x48 ; Slave Config Reg 2 Address Offset
MATRIX_SCFG3_OFS EQU 0x4C ; Slave Config Reg 3 Address Offset
MATRIX_SCFG4_OFS EQU 0x50 ; Slave Config Reg 4 Address Offset
MATRIX_PRAS0_OFS EQU 0x80 ; Priority A for Slave 0 Address Offset
MATRIX_PRAS1_OFS EQU 0x88 ; Priority A for Slave 1 Address Offset
MATRIX_PRAS2_OFS EQU 0x90 ; Priority A for Slave 2 Address Offset
MATRIX_PRAS3_OFS EQU 0x98 ; Priority A for Slave 3 Address Offset
MATRIX_PRAS4_OFS EQU 0xA0 ; Priority A for Slave 4 Address Offset
MATRIX_MRCR_OFS EQU 0x100 ; Master Remap Control R Address Offset
EBI_CSA_OFS EQU 0x11C ; EBI Chip Select Assign Address Offset
; Constants
EBI_CS0_ADDRESS EQU 0x10000000 ; Start of memory addressed by CS0
EBI_CS1_ADDRESS EQU 0x20000000 ; Start of memory addressed by CS1
EBI_CS2_ADDRESS EQU 0x30000000 ; Start of memory addressed by CS2
EBI_CS3_ADDRESS EQU 0x40000000 ; Start of memory addressed by CS3
EBI_CS4_ADDRESS EQU 0x50000000 ; Start of memory addressed by CS4
EBI_CS5_ADDRESS EQU 0x60000000 ; Start of memory addressed by CS5
EBI_CS6_ADDRESS EQU 0x70000000 ; Start of memory addressed by CS6
EBI_CS7_ADDRESS EQU 0x80000000 ; Start of memory addressed by CS7
;// <e> Bus Matrix (MATRIX)
MATRIX_SETUP EQU 0
;// <h> Bus Matrix Master Configuration Registers
;// <h> Bus Matrix Master Configuration Registers 0 (MATRIX_MCFG0)
;// <o0.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// <h> Bus Matrix Master Configuration Registers 1 (MATRIX_MCFG1)
;// <o1.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// <h> Bus Matrix Master Configuration Registers 2 (MATRIX_MCFG2)
;// <o2.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// <h> Bus Matrix Master Configuration Registers 3 (MATRIX_MCFG3)
;// <o3.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// <h> Bus Matrix Master Configuration Registers 4 (MATRIX_MCFG4)
;// <o4.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// <h> Bus Matrix Master Configuration Registers 5 (MATRIX_MCFG5)
;// <o5.0..2> ULBT: Undefined Length Burst Type
;// <0=> Infinite Length Burst
;// <1=> Single Access
;// <2=> Four Beat Burst
;// <3=> Eight Beat Burst
;// <4=> Sixteen Beat Burst
;// </h>
;// </h>
MATRIX_MCFG0_Val EQU 0x00000000
MATRIX_MCFG1_Val EQU 0x00000002
MATRIX_MCFG2_Val EQU 0x00000002
MATRIX_MCFG3_Val EQU 0x00000002
MATRIX_MCFG4_Val EQU 0x00000002
MATRIX_MCFG5_Val EQU 0x00000002
;// <h> Bus Matrix Slave Configuration Registers
;// <h> Bus Master Slave Configuration Regsiter 0 (MATRIX_SCFG0)
;// <o0.0..7> SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;// <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;// <i> broken by another master trying to access this slave
;// <o0.16..17> DEFMASTR_TYPE: Default Master Type
;// <0=> No Default Master
;// <1=> Last Default Master
;// <2=> Fixed Default Master
;// <o0.18..20> FIXED_DEFMSTR: Fixed Index of Default Master <0-7>
;// <i> This is the index of the Fixed Default Master for this slave
;// <o0.24..25> ARBT: Arbitration Type
;// <0=> Round-Robin Arbitration
;// <1=> Fixed Priority Arbitration
;// </h>
;// <h> Bus Master Slave Configuration Regsiter 1 (MATRIX_SCFG1)
;// <o1.0..7> SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;// <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;// <i> broken by another master trying to access this slave
;// <o1.16..17> DEFMASTR_TYPE: Default Master Type
;// <0=> No Default Master
;// <1=> Last Default Master
;// <2=> Fixed Default Master
;// <o1.18..20> FIXED_DEFMSTR: Fixed Index of Default Master <0-7>
;// <i> This is the index of the Fixed Default Master for this slave
;// <o1.24..25> ARBT: Arbitration Type
;// <0=> Round-Robin Arbitration
;// <1=> Fixed Priority Arbitration
;// </h>
;// <h> Bus Master Slave Configuration Regsiter 2 (MATRIX_SCFG2)
;// <o2.0..7> SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;// <i> When the SLOT_CYCLE limit is reached for a burst, it may be
;// <i> broken by another master trying to access this slave
;// <o2.16..17> DEFMASTR_TYPE: Default Master Type
;// <0=> No Default Master
;// <1=> Last Default Master
;// <2=> Fixed Default Master
;// <o2.18..20> FIXED_DEFMSTR: Fixed Index of Default Master <0-7>
;// <i> This is the index of the Fixed Default Master for this slave
;// <o2.24..25> ARBT: Arbitration Type
;// <0=> Round-Robin Arbitration
;// <1=> Fixed Priority Arbitration
;// </h>
;// <h> Bus Master Slave Configuration Regsiter 3 (MATRIX_SCFG3)
;// <o3.0..7> SLOT_CYCLE: Maximum number of Allowed Cycles for a Burst
;// <i> When the SLOT_CYCLE limit is reached for a burst, it may be
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