register.def

义隆公司eSLZ000 dsp处理芯片一个播放midi的样例程序。

.IFNDEF @_REGISTER_DEF
@_REGISTER_DEF	.EQU	1
;--------------------------------------------------------
;         Address of Special Function Registers
;--------------------------------------------------------
SR                .EQU           0x00 ;  Status register address
BSR               .EQU           0x01 ;  Bank select register address
CPUCON            .EQU           0x02 ;  CPU status control register address

PORTA             .EQU           0x06 ;  Port A address
PORTB             .EQU           0x07 ;  Port B address
PORTD             .EQU           0x08 ;  Port D address
INTF0             .EQU           0x09 ;  Interrupt flag register 0 address
INTF1             .EQU           0x0A ;  Interrupt flag register 1 address

INTE0             .EQU           0x0C ;  Interrupt enable register 0 address
INTE1             .EQU           0x0D ;  Interrupt enable register 1 address

PC                .EQU           0x10 ;  Program counter address
SPA               .EQU           0x11 ;  Stack point address
RCR               .EQU           0x12 ;  Repeat counet address
LCR               .EQU           0x13 ;  Loop counetr address
LSA               .EQU           0x14 ;  Loop start address
LEA               .EQU           0x15 ;  Loop end address
INTP0             .EQU           0x16 ;  Interrupt priority register 0 
INTP1             .EQU           0x17 ;  Interrupt priority register 1

EICON             .EQU           0x19 ;  External interrupt control
FSR               .EQU           0x1A ;  PLL frequency SELECT register address
SPLIM             .EQU           0x1B ;  Stack point limited register address 

PORTC             .EQU           0x20 ;  Port C address

PDIRA             .EQU           0x23 ;  Port A DIR address 
PCON1B            .EQU           0x24 ;  Port B control 1 address
PCON2B            .EQU           0x25 ;  Port B control 2 address
PCONC	          .EQU           0x26 ;  Port C control address
PCOND             .EQU           0x27 ;  Port D control address  

TRL0              .EQU           0x30 ;
TCON0             .EQU           0x31 ;
TRL1              .EQU           0x32 ;
TCON1             .EQU           0x33 ;

TCNT2             .EQU           0x34 ;
TCCR2             .EQU           0x35 ;
TCON2             .EQU           0x36 ;
TCNT3             .EQU           0x37 ;
TCCR3             .EQU           0x38 ;
TCON3             .EQU           0x39 ;

WDTCON            .EQU           0x3E ;  Watch dog timer control register
RTCCON            .EQU           0x3F ;  Real time clock control register

SPICON            .EQU           0x40 ;  SPI control register address by alan 
TDBR              .EQU           0x41 ;  SPI TDBR address
RDBR              .EQU           0x42 ;  SPI RDBR address
SPISR             .EQU           0x43 ;  SPI status address

PWMD              .EQU           0x50 ;
PWMP              .EQU           0x51 ;
PWMCON            .EQU           0x52 ;

DROMD          	  .EQU            0x53 ;  DROM data
DROMLA            .EQU           0x54 ;  DROM low address by alan
DROMHA            .EQU           0x55 ;  DROM high address
DROMCON           .EQU           0x56 ;  DROM control

DACD              .EQU           0x60 ;
DACCON            .EQU           0x61 ;

ADCON             .EQU           0x64 ;  ADC control register address
ADCD              .EQU           0x65 ;  ADC data register address
//
MICCON            .EQU           0x6A ;  MIC front end control register address 

.GLOBAL		  SR,BSR,CPUCON,PC,SPA,RCR,LCR,LSA,LEA
.GLOBAL		  INTF0,INTF1,INTE0,INTE1,INTP0,INTP1
.GLOBAL		  EICON,FSR,SPLIM
.GLOBAL		  PORTA,PORTB,PORTC,PORTD,PDIRA,PCON1B,PCON2B,PCONC,PCOND     
.GLOBAL		  TRL0,TCON0,TRL1,TCON1,TCNT2,TCCR2,TCON2,TCNT3,TCCR3,TCON3
.GLOBAL		  WDTCON,RTCCON,SPICON,TDBR,RDBR,SPISR    
.GLOBAL		  PWMD,PWMP,PWMCON,DROMD,DROMLA,DROMHA,DROMCON   
.GLOBAL		  DACD,DACCON,ADCON,ADCD,MICCON  

.include        "registerbit.def"
.ENDIF